Five cycles of a RISC instruction set

Five cycles of a RISC instruction set

RISC (Reduced instruction set computer, compact instruction set computer) is abbreviated as a thin instruction set. RISC places the effort of executing instructions mainly on the instructions that are often used. This paper mainly introduces the main meanings and contents of the five main executing cc (clock cycle, clocking) in a RISC instruction set.

These five clock cycles are: IF (instruction fetch, fetch instruction), ID (instruction Decode/register fetch cycle, instruction Decode), EX (execution/effective Address cycle, execute), MEM (memory access, RAM-visit), WB (Write-back cycle, write-back).

　　if: According to the memory address stored in the PC (program counter, Programs counter), locate the instruction that the address points to in memory and store the instruction in the register. At the same time, the PC refers to the next instruction, the completion of this operation requires the PC plus 4 (32-bit instruction set as an example, if 64 bits will be added 8).

　　ID : The instruction that the operation obtains from the IF phase. The instruction is decoded to finally find the data stored in the register required by the instruction. If the instruction is only a jump instruction, then at this stage you need to compare the obtained value according to the meaning of the jump instruction, if the comparison result is true then the jump is performed, if the comparison result is false, the jump is not performed, and the next instruction is executed if the instruction needs to fill some bits in the instruction. It is also done in the ID phase, such as populating the high four bits to meet the instruction result of 32 bits, and calculating the address of the instruction that may jump.

　　EX : The ALU (arithmetic logic unit, Arithmetic logic units) evaluates the results of the ID phase. The value of the registers required for the instruction calculation has been obtained in the ID phase, so the values of these registers need to be calculated according to the meaning of the instruction in the ex phase. Calculations vary depending on the instruction. There are three main types of ALU calculation: 1. The ALU calculates the valid address unit based on the address added to the ID, and finally gets the address of the required memory; 2. According to the meaning of the instruction, the value obtained from the register, such as the value of two registers added; 3. The result of the immediate number is calculated based on the value of the register and the added value.

　　MEM: If the current instruction is a load instruction, the corresponding value is obtained from memory based on the memory address computed by ex, and if the current instruction is store, the value of the register is stored in the memory address according to the value of the memory address and register computed by ex. Other directives generally do not design memory accesses.

　　WB: Writes the computed value of the final register to the register file. This operation includes the values obtained from memory and the results obtained by arithmetic operations.

The above five clock cycles are a major step in the implementation of a RISC instruction.

Five cycles of a RISC instruction set