Fmark function of LCM

When I recently debugged the r61509v LCM driver chip, there was a problem of residual image refresh (Tearing effect, that is, Te) on the solid color test screen. The root cause is that the write speed of the image data on the master is inconsistent with that on the LCM screen flushing speed. Specifically, the screen flushing speed is faster than the write speed on the master. Fortunately, many LCM drivers have an fmark pin to synchronize with the master. When fmark sends a signal to the master, the master node starts to write a frame of data, which ensures synchronization between the two sides. First, describe several concepts:

(1) screen flushing speed

Screen flushing rate refers to the refresh speed of LCM. This value is usually set in the initialization code of LCM. For rensa's r61509v LCD driver, setting the 0x0010 register is to set the screen flushing speed. According to the formula: Frame Rate = 678 kHz/{(RTN) * Div * (432 + 8 + 8)}, where 678k is the internal clock source of LCM, RTN is the number of clocks per line, div is the division coefficient, (432 + 8 + 8) is the row pixel. The result is as follows:

0x011f 20Hz, minimum frequency.

0x011a 29Hz
0x0115 36Hz
0x0110 52Hz

0x001c 60Hz
0x0018 70Hz

0x0014 80Hz

The screen flushing rate is too low, which may lead to the phenomenon of flicker. Therefore, it is generally set to 60Hz or above.

(2) Master write speed WR and slice selection CS

These two pin pins are available for each dbi lcm, and they work at the same frequency. Each time the master node writes a frame of data, a chip selection signal is generated, which corresponds to a valid write signal of WR. The write frequency of the master is determined by the working state. For example, when a video is taken, the write speed of the dynamic object is faster than that of the static object.

If the screen is not updated, the LCD will be updated once in 70 ms. If the screen is dynamic, the screen will be refreshed up to 33 Ms. This means that the CS frequency can only be limited to 1/70 to 1/30, 14.28hz to 33.33hz. The maximum frequency is faster than the pal or NTSC frame rate. This ensures that frames are not dropped when the camera is working or playing a video.

(3) fmark Function

To enable fmark, first ensure that the fmark foot of the master is correctly connected to the fmark foot of LCM, and then enable the fmark function of the screen during LCM initialization, ensure that the LCM periodically sends signals to the master and enables the fmark function of the master to ensure that the master receives a fmark signal before writing a frame of data.

The fmark of LCM can be configured with two parameters: one is how many times a screen is flushed to send an fmark signal, for example, you do not have to send a fmark signal each time a screen is flushed, and the fmark signal can be flushed several times; the second is the position parameter of the fmark, which allows the fmark to lag several lines of output, so that the master node can write data to the gram later to avoid te.

For example, in this case, the IC outputs the Te signal after reading the last line of the gram. At this time, BB starts to write the gram. However, it may take another two lines for the IC to start reading data from the first row of the gram, and the write speed of the gram is slower than the speed of the IC reading the gram, the write operation may not start yet. As a result, the read gram exceeds the write gram, so tearing is generated above. To avoid te output too early, causing the writing of gram to start first, a delay should be added to ensure that the writing of gram starts only after the reading of old data starts.

(4) fmark and CS cycles

The root cause of the Te phenomenon is that the speed of the two sides is inconsistent. Specifically, the LCM refresh speed is faster than the data transmission speed of the master, and the speed of the two must be within a certain range. It is only necessary to ensure that the CS cycle is between two te cycles, that is, the CS write frequency cannot be less than 1/2 of the Te read frequency. The fundamental condition for tearing is that there is a crossover between read and write. Generally, the write speed (WR) is slower than the LCD screen flushing speed (TE). As long as the screen flushing position does not exceed the write speed of the gram, no screen switching will occur.
For example, for example, CS is a little shorter than the two te cycles. to refresh the data in two shards, the first shard starts to refresh the screen, indicating that reading the gram starts, and the speed is faster, it reads old data, and then the master starts to write the gram, which is about half as fast as the gram. At this time, it has already finished a batch, and then begins to refresh the second batch, that is to say, you can read and screen the screen from the top of the gram. At this time, the newly written data is read. before writing the gram, the read steps will never keep up with the write steps, tearing will not appear.

If CS is larger than two te cycles and assume it is equivalent to three te cycles, the displayed data is written into gram data only in the third read cycle; the first te reads old data. The second te cycle is not completed yet, but the read step is catching up with the write gram step, as a result, the explicit part is the old part is new, so te appears. This is the essence.

If Te is enabled successfully, teering still occurs (especially when the camera is previewing or playing a video). You can analyze the problem from the following aspects.
1) whether the vertical screen is used horizontally, resulting in inconsistent reading and writing directions of the gram, usually leading to the phenomenon of diagonal line screen cutting.
2) is the clock speed too low, and the FPS is less than 1/2 of the LCM self-fl rate?
3) whether the clock speed is too fast and exceeds the self-refreshing rate of LCM. As a result, when writing a gram, it may catch up with reading from the back, resulting in teering.
(5) Te type

When Te is displayed, the LCD te enabling function of the CPU and the Te function of the LCM driver must be enabled. The TM of LCM can be vsysc, vsync & hsync. The figure is as follows: