8051 principles of asynchronous serial port sending and receiving

8051 principles of asynchronous serial port sending and receiving

8051 principles of asynchronous serial port sending and receiving

• From: Liu Jianwen | academic half-It Ge-Wen
• Author: Liu Jianwen
• Keywords: 8051
  Digital Electronics
  Data Communication
• Permanent Link: http://arttech.us/y-2011/8051-uart-rx-tx.html

Postmeta

Tag: 8051,
Digital Electronics,
Data Communication

The basic principle of asynchronous serial communication is that point-to-point Asynchronization, no clock line, no address, low level as the starting bit, high level idle, the communication parties agree on the same data frame size, in addition, with the same baud rate, the transmission and receiving process goes smoothly. Asynchronous Serial Communication supports dual-line simultaneous transmission and receiving, Which is full duplex communication. The data frame content includes a start bit, a 5-9 Data bit, an optional test bit, and a one-to-two stop bit.

The above is the general principle of asynchronous serial communication, but what is the specific communication process? So we need to take a specific implementation-8051 built-in UART for analysis.

The 8051 built-in UART can work in four modes through software programming: Mode 0, Mode 1, Mode 2, and mode 3. Here, we will briefly analyze the asynchronous communication process using the commonly used 1-8 bit UART with variable baud rate.

The frame size of Mode 1 is 10 bits: one start bit (0) + eight data bits (minimum valid bits first) + one stop bit (1), at the receiver, the stop bit is sent to the serial port's control register scon's rb8. Function Diagram for Mode 1:

[Sending asynchronous serial transmission] is triggered by a "writing to sbuf" signal. Any instruction executed with sbuf register as the target register generates a "writing to sbuf" signal, such as mov subf, a. The "Write sbuf" signal also writes 1 to the ninth digit of the [shift register], and sends a signal to the [TX control unit] to send the request once. The actual start point of data transmission is the arrival of the next sending pulse (TX clock), instead of synchronizing the signal with the "Write sbuf". Let's look at the sequence diagram below. The working pulse of the [TX control unit]-The send pulse (TX clock) is obtained after the clock pulse sent by the system is stretched 16 times by a [four-digit counter, while the [downgrading detection unit (1-to-0)
Transtition detector)] is to directly use the clock pulse sent by the system, so the sampling speed for the received signal (rxd) is 16 times higher than the sending speed.

Because the default output of the [data control line] is low, it is also low after the [and door] is input, and the [send control line] is high by default, after the two inputs A [or gate], the output is high, and the txd idle is high. [TX control unit] In the first send pulse to pull down the send control line, txd emits a low level start bit. After a send pulse, the [TX control unit] pulls the high data line, the output of txd depends on the output of the shift. Then, each time the Tx Control Unit sends a shift pulse, one piece of data is sent to txd. After the data bit is removed from the right side, the left side is moved to 0. When [maximum valid bits] are removed, the left side of the highest valid bits is the ninth bit 1 originally sent, and the remaining bits on the left are all 0. This mode is set to zero.
The detector detects that the [TX control unit] enters the [last send digit] State. After one digit is sent, the high send line is pulled and the stop sign Ti is set, an interrupt request is sent to the MCU. [Send the last digit] The Tenth sending pulse after the "Write sbuf" signal.

[Asynchronous serial transmission reception] is triggered by a hop from 1 to 0 detected on the rxd line by the [lower-down detection unit. It has been pointed out that the lower detection unit samples the rxd at a rate 16 times the baud rate, that is, each sending pulse samples 16 times. When a one-to-zero hop is detected, the four-digit counter of the sub-division is reset because the hop from 1 to 0 may appear in any sampling period, reset the counter to align the edge of the sent pulse and the received pulse to achieve real synchronization. When the counter is reset, 1ffh is written to [input shift register] (input shift register ).

In each receiving pulse, the RX control unit controls the [bit detector] to detect rxd three times in the seventh, eighth, and ninth sampling periods, the detection results must be stable at least twice before being confirmed. Detection is performed three times to eliminate noise. If the value of the first received pulse is not 0, the entire circuit will be reset and return to the initial state of repeated checks on rxd for 1 to 0 hops. If the value is 0, the value 0 is moved to the [input shift register] and the data frame receiving process starts.

The data bit is moved from the right to the [input shift register], and the initial 1 is removed from the left. When the start bit (0) is moved to the leftmost bit (mode 1 is a nine-bit long shift register), The RX control unit is fed back to the [tail bit operation signal], after the last shift and moving to the last position, the RX Control Unit determines whether to load the Nine-bit data into sbuf and rb8 based on whether the following conditions are met, and then pulls the high RI.

• First, rI = 0. This indicates that the interrupt request sent after the previous frame of data is received has been responded, and the data in subf has been removed;
• Second, SM2 = 0 or the receiving stop bit is 1. If the stop bit is not 1, the data frame is incorrect. If the value of SM2 is 0, the target slave in multi-host communication can receive data;

If not, discard the received data frame. No matter whether the data frame is received or not, the entire circuit returns to the initial state of repeatedly detecting whether rxd has a 1 to 0 hop.