[Altera] PLL emulation

EDA Tools:

1, Quartus II 13.1 (64-bit)

2, Modelsim SE-64 10.1c

Time:

2016.05.05

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Often see someone in the tangled PLL simulation matter, because they have never tried. Special test.

One, PLL settings:

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Input signals

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Inclk0: Input clock, set 27M

Areset: Asynchronous input, high effective reset

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Output signals

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C0: Output clock, set 74.25M, and same phase as input clock

Locked: Output lock, high level means the output clock is locked

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Second, the test code is as follows:

1' Timescale 1ns/1ps2 3 ModuleTB;4 5 RegInclk0 =0;6 RegAreset =1;7 8  always#18.519Inclk0 = ~inclk0;9 Ten Initial begin One#Ten; A     Repeat( -) @(Posedgeinclk0); -Areset <=0; - End the  -  WireC0; -  Wirelocked; -  +  - pll_74p25m Pll_74p25m_inst + ( A . Areset (Areset), at . Inclk0 (inclk0), - . C0 (C0), - . Locked (locked) - ); -  -  in Initial begin -#Ten; to     Repeat( $) @(Posedgeinclk0); + $stop; - End the  *  $ Endmodule

Three, the simulation waveform

Brief analysis of Waveforms:

1, from reset to clock lock output, only through 4 clock (of course, this is only a reference value, not necessarily all this number bar);

2, only in the output clock out, locked signal only pull high. Therefore, it can be used as the reset signal (or source) of the system;

3, the reference point of the same phase is the rising edge of the input clock.

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over!

[Altera] PLL emulation