ARM CORTEX-M3 exception priority and interrupt priority for Cmsis RTOS RTX

Typically exceptions include some system exceptions, as well as interrupts.

Exception Type

The CORTEX-M3 processor supports multiple types of exceptions:

1. RESET, NMI, HardWare Fault;
2. Psv,svc and other programmable interrupts;
3. Other programmable interrupts, such as Timer,gpio.

The priority of the 1th class of exceptions is fixed and immutable. Everything else can be modified.

The CORTEX-M3 processor provides the Primask option to block all programmable interrupts, providing faultmask to mask hardware fault and all unshielded interrupts.

Exception Priority

The CORTEX-M3 processor supports Nvic interrupt handling, that is, interrupt nesting processing. The priority of the interrupt is determined by 1 8bit registers, but the arm chip vendor typically implements several of these bits when implemented. ARM requires a minimum of 3 bit implementations. The bit 7 from the register starts from high toward low.

And these bits will be divided into preemption priority, the normal priority level. See:

Preemption priority is the same as if the normal priority of the two interrupts, when the preemption of a low priority interrupt a executes, if the preemption priority high Interrupt B occurs, then the interrupt B will preempt interrupt A, the processor starts to execute interrupt B ISR.

The normal priority is that if the preemption priority of two interrupts is the same, then there is no preemption between interrupts, i.e. one interrupt does not interrupt the processing of another interrupt. However, if two interrupts occur at the same time, the normal priority is high, and the first one is processed.

The smaller the number, the higher the priority.

If the two interrupt preemption priority, the normal priority is all the same, then the interruption number of the small interrupt, will be processed first, but still does not happen preemption.

anomaly Vectors

According to CORTEX-M3 's technical documentation, the exception vector "vector tables" is placed at the beginning of the address 0x4, and the address 0x0 is the initial value of the MSP.

As shown below, exception vectors are placed directly at the address of the exception handler, instead of the jump instruction.

CMSIS RTOS RTX Interrupt Priority

As the arm company later engaged in Cmsis, that is, the cmsis layer added support for the RTOS. So many kinds of rtos can rely on the Cmsis RTOs API to implement.

and arm also put Keil RTX operating system, also converted into support cmsis, called Cmsis RTOS rtx.

In Rtx, Systick TIMER/SVC/PSV interrupt priority is 0xFF (specifically to the hardware, to see the chip vendors to achieve 8bit priority of a few bit), so in fact, their priorities are the same, and do not preempt each other.

Users can configure other programmable priorities, not to be

ARM CORTEX-M3 exception priority and interrupt priority for Cmsis RTOS RTX