Assembly Language Learning Note (12) Internal interrupt

Interrupt: Is an important technique for CPU to handle external emergencies.
External interrupts: Interrupts that can be shielded (keyboard interrupts, printer interrupts, etc.)
Internal interrupt: Due to hardware error or operation error, etc.

Based on the interrupt type code, locate the interrupt handler and need to know its segment address and offset address
Access to interrupt handlers can be found through the interrupt vector table
Interrupt vector table specified for storage at memory address 0
256*4=1024 bytes (CS:IP)

In the interrupt process, you need to set the value of the TF and if of the flag register to 0

The interrupt process is as follows:
Get Interrupt Type Code n
Pushf
Tf=0,if=0
Push CS
Push IP
(IP) = (n*4), (cs) = (n*4+2)

General steps:
1) The register used for saving
2) Processing interrupts
3) Recovery of registers used
4) return with iret instruction
Iret: The function of instruction is described in assembly language:
Pop IP
Pop CS
Popf

Iret typically used in conjunction with a hardware auto-complete interrupt process
In the interrupt process, register in the stacking order: Flag Register, CS, IP
and the Iret stack order: IP, CS, flag register
After execution, the CPU returns to the program that resumes execution before the interrupt handler is executed

The do0 can be placed in 0000:0200, and the entry address of the do0 is placed in the interrupt vector table
How long is a code snippet:
Do0end:nop;do0end do nothing, just make a label
Offset Do0end-offset Do0
Set the vector table:
MOV ax,0
MOV Es,ax
mov word ptr es:[0*4],200h
mov word ptr es:[0*4+2],0

Single-Step interrupts:
If the flag register TF bit is detected as 1, a single-step interrupt is generated, causing the interrupt process to occur.
You should not separate the settings of SS:SP