Chisel Tutorial (vii)--module

The following content is based on 2015-7-10 version of Chisel 2.2 Tutorial Finishing

the modules in the chisel are very similar to those in the Verilog HDL , which describe the circuit in a hierarchical structure. the module in Chisel is a class whose definition follows the following points:

• Inherit from Module class
• There is a port named io
• Connecting a sub-circuit in its constructor

The following is a module definition for a 2-select 1 selector:

Class Mux2 extends module{  val io = new bundle{  val sel = UInt (input, 1)  val in0 = UInt (input, 1)  Val in1 = UINT (INPUT, 1)  val out = UINT (OUTPUT, 1)  }  io.out: = (Io.sel & io.in1) | (~io.sel & Io.in1)}

an Operator ": =" in chisel is used inside the module toconnect the right output to the input on the left.

Hierarchy of modules

You can now use submodule building blocks to implement the hierarchy of the circuit, and here is an example of a 4 input selector, built with three 2 input selectors.

Class Mux4 extends module{  val io = new bundle{  val in0 = UInt (input, 1)  val in1 = UINT (input, 1)  Val in2 = UINT (input, 1)  val in3 = UINT (input, 1)  val sel = UINT (input, 2)  val out = UINT (OUTPUT, 1)  }  Val M0 = Module (new Mux2 ())  M0.io.sel: = Io.sel (0)  m0.io.in0: = Io.in0 m0.io.in1  : = Io.in1  val m1 = module (NE W Mux2 ())  M1.io.sel: = Io.sel (0)  m1.io.in0: = io.in2 m1.io.in1  : = io.in3  val m2 = Module (new Mux2 ()) C17/>m2.io.sel: = Io.sel (1)  m2.io.in0: = M0.io.out  m2.io.in1: = M1.io.out  io.out: = m2.io.out}

In the example above, three Mux2 submodules were created, and then the three modules were joined together to form a 4 input selector.

Copyright NOTICE: This article for Bo Master original article, without Bo Master permission not reproduced.

Chisel Tutorial (vii)--module