DDR3 basic knowledge and test "turn"

Transferred from: http://blog.csdn.net/myarrow/article/details/7847385

I. Introduction of DDR3

DDR3 (double-data-rate three synchronous dynamic random access memory) is a high-bandwidth parallel data bus used in the field of computer and electronic products. DDR3 inherits and develops on the basis of DDR2, and its data transmission speed is twice times of DDR2. At the same time, the DDR3 standard allows the capacity of a single memory chip to be expanded to 512Mb to 8Gb, allowing the capacity of the DDR3 chip to be extended up to 16GB. In addition, the operating voltage of the DDR3 is reduced to 1.5V, which is about 30% less than the 1.8V DDR2. In the final analysis, the most technically important support for these indicators is the increase in chip manufacturing processes, with 90nm and even more advanced 45nm manufacturing processes making the same-function MOS tubes smaller, resulting in faster, more dense, more power-saving technology improvements.

The development of DDR3 was not a smooth one, although it had been released in 2005 and applied to the Intel P35 "Bearlake" chipset in 2007, but did not replace DDR2 as quickly as the industry had expected, This middle also experienced to the SDRAM industry far-reaching financial crisis, not only make DDR3 occupy the market speed more slow, but also make DDR3 in the technology once walk in the world's leading memory giant dream Tatsu collapse, it is very regrettable. Nonetheless, DDR3 is now the fastest mature standard in the parallel SDRAM family, and the JEDEC standard specifies a maximum speed of DDR3 up to 1600mt/s (note that 1mt/s is 1 million transmissions per second). In addition, memory vendors can produce DDR3 products that are faster than JEDEC standards, such as DDR3 products at speeds of 2000mt/s, and even reports that their maximum speeds can be as high as 2500mt/s.

Second, DDR memory characteristics
1) The rising and falling edge of the clock transmits data simultaneously

The main advantage of DDR memory is the ability to extract data at both the rising and falling edges of the clock cycle, thereby increasing the data rate of a given clock frequency by 1 time times. For example, in a DDR200 device, the data is transmitted at a frequency of around a-MHz, while the bus speed is.

2) Low operating voltage
The voltages of the DDR1, DDR2, and DDR3 memory are 2.5, 1.8, and 1.5V respectively, so they generate less heat and are more efficient in power management than normal SDRAM chipsets with 3.3V.

       3)   delay small
       Latency is another feature of DDR memory. Memory latency can be represented by a number of numbers, such as 2-3-2-6-T1, 3-4-4-8, or 2-2-2-5 for DDR1. These figures indicate the number of clock pulses required for the memory to perform an operation, the smaller the number, the faster the storage.
      These numbers represent the following actions: Cl-trcd–trp–tras–cmd. To understand them, you must keep in mind that the memory is organized internally as a matrix, and the data holds the intersection of rows and columns.
     CL: Column address strobe (CAS) delay, which is the time between data memory requests from the processor and memory returned.
     TRCD: The delay of the Line address Strobe (RAS) to CAS, which is the time between the Activation Line (RAS) and the Activation column (CAS), where the data is saved in the matrix.
     Trp:ras The pre-charge time, which is the time between disabling data row access and starting another row of data access.
     Tras: Activates the pre-charge delay, which is the time that the memory must wait before starting the next memory access.
     cmd: The command rate is the time between the storage chip activation and the first command sent to the memory. Sometimes, this value is not advertised. It is usually T1 (a clock speed) or T2 (2 clock speed).

Third, the memory of the working speed
Memory technology has evolved from the SDR,DDR,DDR2,DDR3, with the exponential increase in transmission speed, in addition to the lifting factors of the wafer fabrication process, as well as the use of double Data rate and the prefetch two technology. In fact, either SDR or DDR or DDR2, 3, the core clock inside the memory chip is basically consistent, from 100MHz to 200MHz (with the exception of overclocking memory produced by some manufacturers). DDR is a double data rate technology that enables data transfer speeds that are up to one-fold higher than SDRs. As shown, the SDR transmits data only on the rising edge of the clock, while the DDR transmits the data simultaneously on and down the clock signal. For example, the same as 133MHz clock, DDR can achieve the 266mb/s of the digital transmission speed.

Double Data rate technology is a time-out speed, and the speed of data transmission inside the chip is improved by prefetch technology. The so-called prefetch is simply to address multiple storage units at the same time in a single kernel clock cycle and transfer the data in parallel to the IO buffer, then transmit the data in IO buffer at a higher outgoing speed. This higher speed is achieved by double Data rate on DDR I, and because of this, the frequency of the external clock pin of the DDR I is consistent with the core frequency inside the chip. As shown in the prefetch process of DDR I, in a 16-bit memory chip, 2 16bit data is transferred from the core to the external MUX unit at one time, and then two times on the upper and lower edge of the clock signal, the 2 x 16bit data is transmitted to the North Bridge or other memory controller, The whole process goes through exactly one core clock cycle.

To DDR2, the chip core prefetch 4 times times the data to IO buffer, in order to further improve the outgoing speed, the core clock of the chip and the external interface clock (that is, we usually touch the clock pin clocks) is no longer the same as 1:, The external clock clock frequency changes to twice times the core clock. Similarly, DDR3 each time prefetch 8 times times the data, its chip clock frequency is 4 times the core frequency, that is, the JEDEC standard (jesd79-3) specified 400MHz to 800MHz, coupled with the clock signal, the lower jump along the edge of the transmission of data, The data transfer rate of the DDR3 reaches 800mt/s to 1600mt/s. Specific to the memory bar speed, we take pc3-12800 as an example, the core frequency of the ddr3-1600 chip is 200MHz, after prefetch clock signal frequency reaches 800MHz, and then after double Data Rate after the chip data transmission rates are mt/s, the memory bar each transmission 64 bits or 8 bytes of data, 1600x8 will get 12800mb/s peak bit rate.

The following table lists the DDR3 chip and memory-related parameters specified by the JEDEC standard (jesd79-3). It should be noted that, as mentioned earlier, not all memory products are fully compliant with JEDEC standards, some manufacturers will produce faster DDR3 chips, typically these chips are filtered from the chip detection process frequency dynamic range of a larger chip, or can be pressurized overclocking work chip.

Iv. differences between DDR3 and DDR2

The difference in data rates is the most significant difference between DDR3 and DDR2, which is described earlier in this section, and we look at other differences.

In terms of power supply, the operating voltage of the DDR3 is reduced to 1.5V, in fact the JEDEC standard specifies that 1.575V is the maximum safe operating voltage of DDR3. In addition, the standard also stipulates that the memory bar can withstand the safety of the supply voltage must be greater than 1.975V, of course, at this voltage, the memory bar may not work properly but not damaged.

The asynchronous reset signal is introduced in the chip-level DDR3, which mainly provides two functions, one is to simplify the initialization of the memory chip after power-on, and the other is when the memory system enters an unknown or uncontrolled state can be directly reset without power-down restart.

In terms of interface, the common Un-buffer memory strip for example, DDR3 and DDR2 are 240 pin feet, the size of the same, but the position of the anti-slot is different, because the operating voltage is not compatible with the electrical characteristics of the two.

The biggest difference between DDR3 and DDR2 in system design is that DDR3 moves the terminating resistor of the clock, address, and control signal line from the computer motherboard to the memory strip, so that no termination resistors are required on the motherboard. To minimize signal reflection, all control lines, including clock lines on the memory strip, are fly-by topologies. At the same time, it is also because the fly-by line structure causes the control signal line to reach the length of each memory particle, resulting in inconsistent signal arrival time. This situation will affect the memory read and write process, for example, in the read operation, because the read command from the memory controller sent to each memory chip in different points of time, will cause each memory chip to send data to the controller at different times. In order to eliminate this effect, it is necessary to compensate for the time when the memory is read and written, and this will be done by the memory controller. The system framework for the DDR3 bus is shown, where the red line represents the DQ, DM, and differential DQS signal lines, the black line represents the clock, address, and control signal lines, and T represents the corresponding terminating resistor.

Five, DDR3 test
The DDR3 tests specified in the JEDEC standard are divided into three main areas, namely:

• Clock test
• Timing Test
• Electrical Performance Test

The clock test mainly tests the clock signal period, up and down along the pulse width, the period jitter and the continuous n-period cumulative error and other indicators; Timing test mainly test data reading and writing of the establishment of time-dependent parameters; Electrical performance test mainly test signal integrity related indicators, mainly including the slope of each signal and the direct/AC logic high/ Low-power equality indicators. The complete DDR3 test project not only has a wide range of complex judgment processes such as signal reading and writing separation, but manual measurement is not only time consuming but also difficult to ensure the accuracy of measurement. For this purpose, the Force Division has introduced the latest QPHY-DDR3 Automation test package, which will help users complete a complete set of testing tasks from the lap of measured signals, signal acquisition and read-write separation, automated test and analysis to final test report generation with a graphical interface.

Vi. Conclusion
It can be expected that DDR3 will accelerate the capture of more market share in the next two years, Intel's Core i7 processor and AMD's Phenom II processor are built-in memory controllers and support DDR3, while the Core i7 processor will not support DDR2.

Vii. Reference Documents
1. DDR3 SDRAM Standard Jesd79-3d,jedec, September 2009

Transferred from: http://frankielecroy.spaces.eepw.com.cn/articles/article/item/84274

DDR3 basic knowledge and test "turn"