DDR3 Introduction (i)

JEDEC was established in 1958 as part of the Association of Electronic Industry Associations (EIA) to set standards for the emerging semiconductor industry. Key features include terminology definitions, product characterization, test methods, solid state memory, DRAM, flash memory cards, and RFID tags for identification and standardization.

In the DDR2 era, the maximum operating frequency of JEDEC's DDR2 was 800MHz, but many module manufacturers introduced ddr2-1200 and ddr2-1333 memory. In this case, DDR3 memory competitiveness is not high, because the frequency is improved, DDR3 memory delay unit also increased.

Memory latency is generally what we call timing, such as the standard timing of ddr2-800 memory: 5-5-5-18, but the standard timing of ddr3-800 memory reaches 6-6-6-15. These four parameters

Represents several important aspects of the DDR timing, all of which are in the number of clock units. CAS Latency (CL) memory CAs delay time, in turn, for read operations only; Ras-to-cas delay

(TRCD) The time that the memory line address is transmitted to the column address, the row precharge delay (TRP) memory pre-charge time, and the row-active delay (TRAS) Memory line address is selected.

DDR3 These parameters will be larger than DDR2, but it is not said DDR3 delay will be greater than DDR2, because the clock frequency of DDR3 is also relatively high, so the final absolute delay DDR3 Also

is relatively small. And the JEDEC set memory timing is conservative, memory module manufacturers will introduce low-latency DDR3 memory.

DDR3 memory bandwidth greatly improve, or rely on data prefetching prefetch, to the DDR3 era, prefetch technology developed to 8Bit, one can pre-fetch 8Bit data from the storage unit,

At both the upstream and downstream of the input and output ports, the 8Bit requires 4 full clock cycles, so the input and output clock frequency of the DDR3 memory is 4 times times the core of the storage unit. Effective data transmission Frequency

The rate is 8 times times the core frequency of the storage unit. The storage core frequency of ddr3-800 memory is only 100MHz, the input and output frequency is 400MHz, and the effective data transmission frequency is 800MHz. In implementing

In the process of prefetch, the internal bus bit width of the storage unit is also increasing, such as the internal bus bit width in the DDR3: Chip bit width =8:1.

The core operating voltage of the DDR3 becomes 1.5V, where the ddr3l low version is 1.35V and the DDR2 operating voltage is 1.8V. Voltage reduced by 17%.

Several new features of DDR3: Reset function, which is an important feature added in DDR3 memory. It makes the initialization of DDR3 memory simpler and more convenient for power control.

Auto-Refresh (Automatic self-refresh) function, which controls the refresh frequency with a temperature sensor built into the DDR3, so as to ensure that the data is not lost

Reduce the refresh rate. The partial self-refresh feature, an option for DDR3 memory, refreshes only part of the logical bank, reducing the power consumption caused by the flush operation.

DDR3 's memory particle density is much larger than DDR2, and the logical bank starts from 8bank, the total memory can reach 8G, and supports 64-bit data lines. and DDR2 's logos

The bank is generally 4bank, the total memory can reach 4G.

DDR3 Introduction (i)