in the design of the PCB of the DDR, it is generally necessary to consider the equal length and topological structure. Equal length is better to deal with, given a certain length of the accuracy of the PCB designer is usually able to complete. But for different rates of DDR, it is critical to choose the right topology, the T-topology and the daisy-chain topology that are often used in DDR cabling, and the differences and attention points of the two topologies are described below.
T-type topological structure, also known as a Star topology, is shown in its structure. Star topology Each branch of the receiving side load and the length of the line as far as possible to maintain the same, this ensures that each branch receive the load at the same time to receive signals, each branch generally requires a terminal resistor, the resistance of the terminal resistor should be matched with the characteristic impedance of the connection. Star topology can effectively avoid the clock, address, and control signal of the different-step problem.
Figure A
Daisy Chain Topology, shown in two. Unlike star topologies, the daisy-chain topology does not keep the drive-to-load line lengths as consistent as possible, but ensures that the lengths of each drive end to the signal main road are as short as possible. The characteristic of the line of the chain topology is that the synchronization of clock, address and control signal is sacrificed, but the most important feature is to minimize the length of each load branch line and avoid the interference of branch signal to the main signal.
In the case of signal frequency below 800MHz, the above two topologies can meet the requirements of system performance. But when the signal rate reaches 1000MHz or higher, the T-type topology does not meet the performance requirements. The reason lies in the long Branch length of the T-type topological structure, it is difficult to achieve impedance matching with the main road without adding the terminal resistor, and in order to achieve the impedance matching of each branch to add the terminal resistor, but also increased the workload and cost of circuit design, we do not want to see. Therefore, the high-speed signal uses the T-type topological structure, the branch signal to the main signal reflection interference is very serious. The T-type topology is typically used for DDR3 with low DDR2 and rate requirements. Daisy chain topology is mainly used in DDR3, the main advantage of the chain topology is that the branch line is short, it is generally believed that the length of the daisy chain branch line is less than 1/10 of the signal rising along the length of the transmission, can effectively weaken the branch signal reflection on the main signal interference, different books on the same way, In general, the length of the line is less than the rising edge of the propagation length of the 1/6-1/10 is possible, the actual design we certainly hope that the shorter the better. The daisy-chain topology can effectively suppress the reflected signal of the branch, but the clock, address and control signal of the daisy-chain topology cannot reach different DDR chips in relation to the T-type topological structure. In order to solve the problem of the signal synchronization in the daisy-chain topology, the new standard of DDR3 adds the time compensation technology, which realizes the signal synchronization through the DDR3 internal adjustment. When the signal frequency of up to 1600MHz, T-type topology has been powerless, only the daisy chain or its derived topology can meet such performance requirements. The general DDR3 will recommend an improved topological structure with a daisy-chain topology, fly-by topology, as shown in three. The fly-by topology requires the branch wiring length stub=0,fly-by to have better signal integrity.
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DDR cabling requirements and topological structure analysis
