DDR parameter settings for the I.MX6 Development Board-Schindler

the DDR Stress Test Tool provides two purposes. First, it can be used to calibrate the DDR3 so that the MMDC PHY delay settings and PCB are paired to achieve the best dram new energy. The whole process is fully automated, so customers can get their DDR3 working in a short period of time. In addition, the tool can run memory stress tests to verify the functionality and reliability of the DDR3. Stress tests can be used to verify hardware connections, MMDC register parameters, and DDR3 mode register settings. The most important purpose of testing is to have the customer verify that the DDR3 is running stably on their own board.
calibration in I. On the MX6 processor, the DDR3 requires 4 calibration procedures, which fine-tune the MMDC PHY wait register correction to type the DDR3 configuration in the DDR Stress Test tool. First, the calibration test will indicate the DRAM frequency. The default values for I.mx6q and i.mx6d are the default values of 528MHZ,I.MX6DL, i.mx6s, and I.MX6SL are 400MHz. This is the DRAM frequency used by the BSP. Press ' Y ' to proceed with the correction process. The input ' n ' here will have an option to select a specific frequency. It's just for debugging. After the DRAM frequency selection is over, the tool will start correcting.

Write Leveling Calibration
This is the first correction to be used to fine tune from I. MX6 the delay between the DRAM clock and write DQS output processor, press ' Y ' to proceed with the correction process. If the board has been corrected and the correction result has been and is integrated into the script, press ' n ' to skip the correction. After you start the correction by pressing ' Y ', you need to enter the value of DDR3 Mode Register MR1, and the value of MR1 can be found in the following line of the initialization script. The value is the two most significant byte after the equal sign, i.e. 0x0004 on this example.
setmem/32 0x021b001c = 0x00048031//MMDC0_MDSCR, MR1 write, CS0 the value must be the same as in the DDR initialization script. Otherwise, the following test result will be invalid, because the value is used to restore DDR3 's MR1 value when exiting write leveling mode.

Read DQS gating Calibration
The second correction process is DQS gating calibration. It is used to fine-tune the read DQS gating so that it can accurately capture the read DQS signal. The calibration program adjusts the DQS gating delay to find a valid DQS delay window in the 4/256-always cycle. Press ' y '/' n '
Intermediate operation similar, no longer translated

Calibration Results
After finishing all the calibration process, the calibration results is summarized and as shown below.? The tool would proceed to run the DRAM stress test with the delay registers updated with these calibration results.

However, it's very important that these results should being recorded down and the DRAM initialization script should be Updated accordingly. When porting the MMDC parameters to the firmware, the delay registers must is programmed according to the updated script. Otherwise, the DDR3 May is able to run stably on the firmware.
in general, the operation process is as follows: using the aid tool provided by Freescale (Excel) to generate an. inc file based on your board's selection and design, this part of the Freescale will help, just provide the design material to AE using DDR Stress test tool to correct the generated parameters on your board based on the test results, fix your. inc File and Stress test add the data from the Inc file to the U-boot Flash_header.s.

DDR parameter settings for the I.MX6 Development Board-Schindler