DDR technology and HSTL level (zz)

Abstract: The DDR technology and HSTL level standard are high-speed data transmission technologies that have emerged in recent years. The specific use of these two technologies in ddr sram devices is discussed based on actual issues.

Keywords:Ddr sram hstl level

Samsung ddr sram is one of the fastest in the world. Because of its special level characteristics and high-speed characteristics, the design of the reading circuit is different from that of traditional SRAM. This paper describes the application of this new high-speed SRAM device and discusses a rare level standard HSTL.

1 HSTL level

1.1 Basic Definition

HSTL (high speed transceiver logic) is a circuit logic standard officially developed in 1995 by JEDEC (Joint Electron Device Engineering councer.

HSTL is a technically independent digital integrated circuit interface standard developed to achieve voltage expansion and technology independent I/O structure. The I/O structure required by this standard is a differential amplification input (an input is internally associated with an input reference voltage provided by a user for single-ended input) and an output using vcco. The so-called technology independence actually refers to the voltage used for input reference and output of vcco, which is different from the power supply voltage of the device itself.

The main application of HSTL is that it can be used for high-speed memory reading. The traditional slow memory access time hinders the operation of high-speed processors. In the intermediate frequency (between MHz and MHz), you can choose an I/O structure based on single-ended signals: HSTL, GTL/GTL +, SSTL, and low-voltage TTL (lvttl ). In the range above MHz, the HSTL standard is the only available single-ended I/O interface. With the speed of HSTL, the fast I/O interface significantly improves the performance of the entire system. HSTL is an I/O interface choice for high-speed memory applications. It also perfectly provides the ability to drive the address bus of multiple memory modules.

1.2 category

In the HSTL standard, HSTL is divided into four types based on different output buffer characteristics. Among them, 1st, 3, and 4 are parallel terminal loads, and 2nd are serial terminal loads. Here, only 1st types of loads are provided. For other loads, refer to the references in this article.

The level properties of the HSTL-I are shown in table 1.

Table 1 HSTL-I Input and Output Basic parameters

Parameter	Minimum value	Typical values	Maximum Value
Vcco Vref VTT VIH Devil Voh Vol Ioh at voh (MA) Intraocular lens at vol (MA)	1.40 0.68 - Vref + 0.1 - VCCO-0.4 - -8 8	1.50 0.75 Vcco x 0. 5 - - - - - -	1.60 0.90 - - VREF-0.1 - 0.4 - -

The load 1 of the HSTL-I is shown.

It can be seen that the HSTL-I needs to use a 50Ω resistor to balance the transmission line impedance, but also an external VTT to provide up-pull voltage.

2 DDR SRAM

To meet the hardware design requirements, Samsung ddr sram (k7d801871b), the world's fastest SRAM device, was selected ). The device is KB × 18 ddr sram and uses the HSTL level standard. Its fastest model can work at 333 MHz, and its maximum data read rate is 666 MHz.

Familiar with DDR technology, ddr sdram began to enter the PC and compete in the memory market. The DDR technology is also proposed as the next generation high-speed memory standard. Specifically, the DDR technology uses the rising and falling edges of the clock to perform data read/write operations, instead of performing data read/write operations only once in a previous clock cycle, this is also the origin of the DDR (double data rate, double data rate) Name. From the perspective of chip technology development, it is difficult to increase the clock frequency of the memory chip. In particular, it is necessary to work with other devices and it is impossible to increase the clock frequency. Using DDR technology, we can increase the data transmission rate to twice the theoretical value without increasing the clock frequency. Therefore, DDR technology has been widely used in memory such as SDRAM and SRAM, and QDR (quad data rate) is also used to further improve the transmission speed.

In order to accurately use the rising and falling edges of the clock during data input, the clock of ddr sram requires a differential input, that is, two clock inputs (K, K #) for mutual inversion #). In addition, to accurately match the rising and falling edges of the clock, ddr sram provides two output clock signals (C, C #) for mutual inversion #).

The internal system structure 2 of ddr sram is shown in.

3. Connect the SRAM to the common TTL circuit

3.1 system requirements

In this project, the front-end sampling data is read to the PC through the PCI interface. This method is also used to achieve high-speed data stream read/write; select PLX PCI9054 to connect the PCI interface to the local circuit. PCI interfaces (including PCI9054) Use TTL levels (5 V and 3.3 V), while data is stored in ddr sram using HSTL levels, this requires that there must be a level conversion in the PCI interface circuit and ddr sram.

Table 2 and table 3 provide the level characteristics of TTL and HSTL respectively.

Table 2 TTL level (unit: V)

Letter Number	Minimum	Largest
Voh Vol VIH Devil	2.4 - 2.0 -0.5	- 0.4 5.5 0.8

Table 3 HSTL level (unit: V)

Signal	Minimum	Max	Typical	Test conditions
Voh	1.3	1.5	-	Vddq= 1.5 Vref = 0.75 VSS = 0 Non-variable Impedance
Vol	0	0.2	-
Devil	-0.3	0.65	0.25
VIH	0.85	1.8	1.25

3.2 FPGA connection

Some Logical Circuits are required to connect the PCI interface and ddr sram, and PLD is used for debugging and modification. According to research, currently, mainstream FPGA vendors Xilinx and Altera provide support for HSTL level in their large-capacity FPGA products. Among them, Xilinx's Virtex series (including Virtex, Virtex-E, Virtex-II) and Altera's apex series (including apex and apex II) can both support HSTL levels, DDR logic is also supported. Therefore, FPGA is used to connect ddr sram and PCI9054, avoiding the need to build a level conversion circuit. For the 32-bit address/Data circuit used, the number of devices required for the level conversion circuit of discrete devices is large, which is not conducive to the design and wiring of boards.

Figure 3 shows the structure of FPGA's actual logic. In Figure 3, the relay is used in combination with other parts of the circuit.

Figure 4 is the hstl I/O device symbol in the Xilinx Virtex series. In addition, there are dedicated input/output devices, which are omitted here. It can be seen that this is a three-state I/O port, the IO end is connected to the fpga I/O port, the I and o end are connected to the output and input logic circuits respectively, and the T is similar to the bus switch, determines whether the output is in a high-impedance state.

Ddr sram applies many new technologies to improve the transmission rate, so high-speed digital circuit designers have a good choice. As a high-speed standard, HSTL will become more and more widely used by professionals with the application of ddr sram. It is expected that there will be more and more high-speed devices based on HSTL. Understanding and mastering HSTL level and DDR technology are essential skills for high-speed digital circuit designers in the future.