De0-based VGA display driver

Display standard: 800*600 @ 72Hz, 50 m clock frequency.

Device: cyclone3ep3c16484

Software Version: quatus ii9.0

Code:

Top-level module:

Module pika (
Clock_50,
Vga_hs,
Vga_vs,
Button,
Vga_g,
Vga_r,
Vga_ B
);

Input clock_50;
Input [2: 0] button;
Output vga_hs;
Output vga_vs;
Output [3: 0] vga_g;
Output [3: 0] vga_r;
Output [3: 0] vga_ B;

Wire [10: 0] x_addr;
Wire [10: 0] y_addr;
Wire vga_hs;
Wire vga_vs;
Wire ready;
Sync_module U1 (
. CLK (clock_50 ),
. Reset (Button [2]),
. X_addr (x_addr ),
. Y_addr (y_addr ),
. Hsync (vga_hs ),
. Vsync (vga_vs ),
. Ready (ready)
);

Wire [63: 0] rom_data;
Wire [5:0] rom_addr;
Vga_ctrl_module u2 (
. CLK (clock_50 ),
. Reset (Button [2]),
. Ready (ready ),
. X_addr (x_addr ),
. Y_addr (y_addr ),
. Red (vga_r [3]),
. Green (vga_g [3]),
. Blue (vga_ B [3]),
. Rom_data (rom_data ),
. Rom_addr (rom_addr)
);

Rom U3 (
. Address (rom_addr ),
. Clock (clock_50 ),
. Q (rom_data ));
 
Endmodule

 

Synchronization module:

Module sync_module (
CLK,
Reset,
X_addr,
Y_addr,
Hsync,
Vsync,
Ready
);

Input CLK;
Input reset;
Output [5:0] x_addr;
Output [5:0] y_addr;
Output hsync;
Output vsync;
Output ready;

Reg [10: 0] x_count;
Always @ (posedge CLK or negedge reset)
Begin
If (! Reset)
X_count <= 11 'd0;
Else if (x_count = 11 'd1040)
X_count <= 11 'd0;
Else
X_count <= x_count + 1' D1;
End
 
Reg [10: 0] y_count;
Always @ (posedge CLK or negedge reset)
Begin
If (! Reset)
Y_count <= 11 'd0;
Else if (y_count = 11 'd666)
Y_count <= 11 'd0;
Else if (x_count = 1040)
Y_count <= y_count + 1 'd1;
End
 
Assign ready = (x_count> 183 & x_count <983) & (y_count> 28 & y_count <628 ))? 1 'd1: 1' D0;
Assign x_addr = (ready )? X_count-183: 6 'd0;
Assign y_addr = (ready )? Y_count-28: 6 'd0;
Assign hsync = (x_count> 119 )? 1 'd1: 1' D0;
Assign vsync = (y_count> 5 )? 1 'd1: 1' D0;

Endmodule

 

VGA control module:

Module vga_ctrl_module (
CLK,
Reset,
Ready,
X_addr,
Y_addr,
Red,
Green,
Blue,
Rom_data,
Rom_addr
);

Input CLK;
Input reset;
Input ready;
Input [10: 0] x_addr;
Input [10: 0] y_addr;
Input [63: 0] rom_data;
Output [5:0] rom_addr;
Output red;
Output green;
Output blue;

Reg [5:0] rom_adr;
Always @ (posedge CLK or negedge reset)
Begin
If (! Reset)
Rom_adr <= 6'd0;
Else if (ready & y_addr> 300 & y_addr <364)
Rom_adr <= y_addr []-300;
Else rom_adr <= 6 'd0;
End
 
Reg [5:0] rom_data_bit;
Always @ (posedge CLK or negedge reset)
Begin
If (! Reset)
Rom_data_bit <= 6 'd0;
Else if (ready & x_addr> 200 & x_addr <264)
Rom_data_bit <= 263-x_addr [10: 0];
Else rom_data_bit <= 6 'd0;
End

Assign rom_addr = rom_adr;
Assign Red = (ready )? Rom_data [rom_data_bit]: 1 'd0;
Assign Green = (ready )? Rom_data [rom_data_bit]: 1 'd0;
Assign Blue = (ready )? Rom_data [rom_data_bit]: 1 'd0;

Endmodule

Rom module:

Module Rom (
Address,
Clock,
Q );

Input [5: 0] address;
Input clock;
Output [63: 0] q;

Wire [63: 0] sub_wire0;
Wire [63: 0] q = sub_wire0 [63: 0];

Altsyncram altsyncram_component (
. Clock0 (clock ),
. Address_a (address ),
. Q_a (sub_wire0 ),
. Aclr0 (1' B0 ),
. Aclr1 (1' B0 ),
. Address_ B (1 'b1 ),
. Addressstall_a (1 'b0 ),
. Addressstall_ B (1 'b0 ),
. Byteena_a (1 'b1 ),
. Byteena_ B (1 'b1 ),
. Clock1 (1 'b1 ),
. Clocken0 (1 'b1 ),
. Clocken1 (1 'b1 ),
. Clocken2 (1 'b1 ),
. Clocken3 (1 'b1 ),
. Data_a ({64 {1 'b1 }}),
. Data_ B (1 'b1 ),
. Eccstatus (),
. Q_ B (),
. Rden_a (1 'b1 ),
. Rden_ B (1 'b1 ),
. Wren_a (1 'b0 ),
. Wren_ B (1 'b0 ));
Defparam
Altsyncram_component.address_aclr_a = "NONE ",
Altsyncram_component.clock_enable_input_a = "Bypass ",
Altsyncram_component.clock_enable_output_a = "Bypass ",
Altsyncram_component.init_file = "rom_pic_mif.mif ",
Altsyncram_component.intended_device_family = "cyclone III ",
Altsyncram_component.lpm_hint = "enable_runtime_mod = No ",
Altsyncram_component.lpm_type = "altsyncram ",
Altsyncram_component.numwords_a = 64,
Altsyncram_component.operation_mode = "Rom ",
Altsyncram_component.outdata_aclr_a = "NONE ",
Altsyncram_component.outdata_reg_a = "clock0 ",
Altsyncram_component.ram_block_type = "m9k ",
Altsyncram_component.widthad_a = 6,
Altsyncram_component.width_a = 64,
Altsyncram_component.width_byteena_a = 1;

Endmodule

 

Initialize the content of the MB table of the RoM (picaccho ):

0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000180000000000
0000380000000000
20173c0000000000
20177c0000000000
Fc00000000070000
0000fe00003f0000
0000e60001ff0000
0001860007ff0000
0001c6000c3e0000
000101f8701c0000
00018fffe0380000
0001840780300000
0001600000607800
000000000c0c800
0003000001c0cf00
0003003803010780
000f004c160300c0
000d807c1c0300e0
000f007c0c060060
001720109c060060
001a6001060600c0
00180003820c0180
001cffc7c30c0300
001c7707c1b80e00
001c3f07c1181800
00bc1e01f1b01800
00ec0003b1d83000
018200071bcc3c00
0181000219c61600
00c0000000060e00
0060000020371c00
0028000000ac3000
003c0001e1f0e000
0006001b5bfcc000
0003001f03fce000
000100003581fc6000
00010031807fc000
0001000030e07f8000
0001000840f80000
0001c008c0f00000
0000c018c3c00000
2017c01d83000000
2017600e8c000000
201734066c000000
20171e03f0000000
0000070380000000
000001cf00000000
000000e700000000
0000006300000000
0000007e00000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000

 

TCL files allocated by pins:

Set_location_assignment pin_j21-to vga_g [3]
Set_location_assignment pin_k17-to vga_g [2]
Set_location_assignment pin_j17-to vga_g [1]
Set_location_assignment pin_h2-to vga_g [0]
Set_location_assignment pin_l21-to vga_hs
Set_location_assignment pin_l22-to vga_vs
Set_location_assignment pin_h21-to vga_r [3]
Set_location_assignment pin_h20-to vga_r [2]
Set_location_assignment pin_h17-to vga_r [1]
Set_location_assignment pin_h19-to vga_r [0]
Set_location_assignment pin_k18-to vga_ B [3]
Set_location_assignment pin_j22-to vga_ B [2]
Set_location_assignment pin_k21-to vga_ B [1]

Set_location_assignment pin_g21-to clock_50

Set_location_assignment pin_f1-to button [2]

 

It's fun. Oh, it's cute !!!