Depressed, I was blackmailed.

Author: gooogleman Date: 2011.08.31

Yesterday I wanted to reduce the memory frequency by 2416. I started to look at it with 2440 thinking that 2440 of hclk is the memory frequency, so 2416 should be the same. However, TMD 2416 has repeatedly stressed ddrclk in the framework diagram and manual and told ddrclk about it. ddrclk has always been the so-called 266m ...... in the figure, ddrclk and hclk are parallel, and hclk cannot intervene in ddrclk, but ddrclk cannot find the setting, which is amazing.

Samsung is actually used. In the manual, the hclk * 2 in the figure in ddrclk is very small. It is from the picture and cannot be viewed. I only saw it when I enlarged the picture. It was depressing. That is to say, ddrclk is equal to hclk * 2 ?! --------------------- Samsung, you are a zombie!

I didn't expect it to be fooled. The memory frequency of 2416 still comes from the hclk settings. The manual page 672 is as follows:

The AHB and APB clocks are en/disabled by hclkcon register. All reserved BITs have 1 value at initial state.

Hclkcon bit description Initial Value

Reserved [31: 21]-0x7ff

2d [20] Enable hclk into 2D 1

Dramc [19] Enable hclk into DRAM controller 1

Ssmc [18] Enable hclk into the ssmc Block 1

Reserved [17]-1

Hsmmc1 [16] Enable hclk into the hsmmc1 1

Hsmmc0 [15] Enable hclk into the hsmmc0 1

Reserved [14]-1

Irom [13] Enable hclk into the irom 1

USB Dev [12] Enable hclk into the USB device 1

USB host [11] Enable hclk into the usb host 1

Reserved [10]-1

Dispcon [9] Enable hclk into the display controller 1

Reserved [8: 6]-0x3

Dma0 ~ 5 [7:0] Enable hclk into DMA channel 0 ~ 5 0x3f

--------------------------------------------------------------- Another error occurred!

In the SD irom startup code of 2416

Dvson Seta
0

Hclkval Seta
133

Startup_mpll equ
800000000

Startup_mdiv equ
240

Startup_pdiv equ
3

Startup_sdiv equ
2

Startup_armclkdiv equ
0;
0: armclk
= Mpll/1

-- See the following mpll calculation formula:

The output frequencies of mpll can be calculated using the following equations:

Fout = (m x fin)/(P x 2 S

) (Shocould be 40 ~ 1600 MHz)

Fvco = (m x fin)/P (shocould be 800 ~ 1600 MHz)

Where, M = mdiv, P = pdiv, S = sdiv, fin = 10 ~ 30 MHz

ThisStartup_mpll =Fout = (m x fin)/(P x 2 S) = 240*12/(3*2*2) = 240 m impossible to beStartup_mpll
Equ 800000000 !!!

It hurts. No wonderStartup_armclkdiv equ
0;
0: armclk
= Mpll/1. At first, I thought 2416 armclk ran MB. Hey.

Now, check the hclk problem. I hope I can find some problems and solve the problems that some hardware cannot be started and NK. Bin cannot be downloaded.