DRAM is dynamic memory, and its basic unit consists of a transistor and a capacitor. Please see:
The figure is the structure of a basic unit of DRAM: the state of the capacitor determines whether the logical state of the DRAM unit is 1 or 0, but this characteristic of the capacitor is also its disadvantage. A capacitor can store a certain amount of electrons or an electric charge. A rechargeable capacitor is considered a logical 1 in digital electronics, while the "empty" capacitor is 0. The capacitor cannot hold the stored charge for a long time, so the memory needs to be refreshed periodically in order to maintain the data being staged. The capacitor can be charged by the current--of course the current is limited, or the capacitance will be penetrated. At the same time, the charge and discharge of the capacitor will take a certain period, although the capacitance in the basic unit of memory this time is very short, only about 0.2-0.18 microseconds, but this period of memory is not able to perform access operations.
Some information from the DRAM manufacturer shows that memory is refreshed at least once every 64ms, which means that memory has 1% of the time to refresh. Automatic memory refresh is not a challenge for memory vendors, but the key is to keep the contents of the memory intact when the internal storage element reads-so the DRAM unit is refreshed after each read operation: A write-back is performed because the read operation also breaks
Bad memory, which means that the data stored in memory is destructive. So the memory not only needs to be refreshed every 64ms, but also refreshed after each read operation. This increases the cycle of access operations and, of course, the longer the incubation period.
SRAM, Static RAM does not have a refresh problem, an SRAM base unit consists of 4 transistors and 2 resistors. Instead of storing data by using the characteristics of the capacitor charge and discharge, it uses the state of the set transistor to determine the logical state-the same as the logical state in the CPU. The read operation is not destructive to SRAM, so there is no flush problem with SRAM.
SRAM not only operates on clock frequencies higher than DRAM, but is much shorter in latency than dram. SRAM requires only 2 to 3 clock cycles to access the required data from the CPU cache, while DRAM requires 3 to 9 clock cycles (here we ignore the time the signal travels between the CPU, chipset, and memory control circuitry). As mentioned earlier, the number of transistors required by SRAM is 4 times times that of DRAM, which means that the cost is at least 4 times times higher than DRAM, at the current price of SRAM each m is about 8 times times the price of DRAM, which is 2 to 3 times times the Rambus memory. But its very short incubation period and high-speed clock frequency can actually lead to higher bandwidth.
DRAM memory principle (i) Memory basics
