ECC calibration principle and its application in NAND flash

This article mainly introduces the basic principles of ECC and its application in NAND flash, this paper records its understanding and learning of ECC calibration principle.

ECC Introduction

ECC, known as error correcting code, is a coding method that is used to detect and correct errors in the transmission to some extent.

Shannon published in 1948, "Mathematical Theory of Communication," the channel coding theorem pointed out: the main use of appropriate error-correcting code, you can transmit messages on a multi-class channel, the error rate can be arbitrarily small. Through the continuous efforts of successive generations, we have found many good channel coding methods to meet many practical requirements.

When constructing error-correcting code, the input information is divided into K-bit group to encode. If the verification bit is only related to the information bit of this group, such code becomes the block code. If it is not only related to the K information bits in this group, but also relates to the information bits of the previous groups, it becomes convolutional code.

Error correcting code can be detected or corrected, mainly by the difference between the code word. This can be measured by Hamming distance d (x, y). The minimum distance d of an error-correcting code is defined as the minimum distance between any two code words in the code.

A code to be able to find N errors, its minimum distance d should be no less than (n+1),

A code to be able to correct n errors, its bottom distance d should be no less than (2n+1)

Hamming Code Introduction

It is a linear block code that can detect and correct an independent error, using an extra parity bit to identify a bit of error.

1. Mark the data bits of all 2 powers as parity bits (numbered 1, 2, 4, 8, 16, 32, 64, etc.)

2. Other data bits are used for data to be encoded. (numbered 3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 17, etc.)

3, the value of each parity bit represents the parity of some bits of data in the code word, where the position determines the bit order to be verified and skipped.

Position 1: Check 1 bits, skip 1 bits, check digit number is: 1,3,5,7,9,11,13,15,...

Position 2: Check 2 bits, skip 2 bits, check digit number is: 2,3,6,7,10,11,14,15,...

Position 4: Check 4 bits, skip 4 bits, check digit number is: 4,5,6,7,12,13,14,15,20,21,22,23,...

Position 8: Check 8 bits, skip 8 bits, check digit number is: 8-15,24-31,40-47,...

If there is an odd number of 1 in the position of the checksum, the parity position is 1, if there is an even number of 1 in the position of the checksum, the parity position is 0.

As shown in the following:

Example: A byte of data 1001_1010, as shown, d[0]~d[7] fill in the corresponding value, D[0] Write 1,d[1] Write 0 ...., you need to calculate 4 check bits, according to the above principle:

C[0] = d[0] xor d[1] XOR d[3] XOR D[4] xor d[6] = 0

C[1] = d[0] xor d[2] XOR d[3] XOR d[5] XOR d[6] = 1

C[2] = d[1] xor d[2] XOR d[3] XOR d[7] = 1

C[3] = d[4] xor d[5] XOR D[6] xor d[7] = 0

The result of the final arrangement is: 011100101010, this code word represents the 8-bit real code plus 4-bit redundancy code, can be self-correcting a mistake. That is, in the transmission process, this code word, regardless of which one appears bit flip, at the receiving end can be detected and corrected back.

This column data is received at the receiving end, or according to the method described above, see m[0] and M[2] XOR M[4] XOR m[5] XOR M[6] XOR m[10] is equal, if equal, set to m[0] bit set to 0, unequal sets the corresponding bit to 1.

By this calculation four times, get M[7] m[3] m[2] m[0], if the transmission is correct, then the four bits are 0. If a person flips, such as m[4], an error occurs, from 0 to 1, then the parity of m[0] and the m[3] is calculated as an error, then

M[7] m[3] m[1] m[0]

Correct 0 0 0 0

M[4] Error 0 1 0 1 ==> for the fifth number in the accepted sequence, i.e. m[4]

M[7] Error 1 0 0 0 ==> for the eighth number in the accepted sequence, i.e. m[7]

Scope of application

The error-correcting code transmits all digital signals. This is either hardware-enabled or software-enabled. The former mainly use a variety of digital circuits, mainly using large-scale integrated circuits. Software implementation is particularly suitable for computer communication networks and other occasions. Because this can directly use the computer in the network to encode and decode, do not need additional special equipment. The hardware is implemented at a high speed and can be several orders of magnitude faster than software.

In the case of certain communication rate, if the error correcting code is used to improve the reliability, the transmission rate of the channel is increased and the bandwidth increases. Therefore, the error correcting code is mainly used in the channel with limited power and large bandwidth, such as satellite, scattering and other systems. Error correcting codes are also used in some reliability requirements, but the reliability of the device or device is poor, and large headroom, such as tape, disk and semiconductor memory.

Applications in Nand Flash

Due to the NAND flash process, there is no guarantee that the memory array in NAND can maintain reliability in the life cycle, therefore, in the use of the process will produce bad blocks, in order to ensure the reliability of the data, Nand Flash controller generally built a bad fast management strategy. If there is no problem with operation timing and circuit stability, Nand Flash error generally does not cause an entire block or page error, but one or a few bits of the entire page error.

In NAND flash processing, using a dedicated checksum method, ECC, which corrects single-bit errors and detects double-bit errors, is computationally fast. In the case of Samsung Flash, a piece of NAND flash is a device, 1 (device) = xxxx (Blocks), 1 (Block) = xxxx (Pages), 1 (Page) =528 (Bytes) = data block Size (512 Bytes) + OOB block Size (16Bytes, in addition to the OOB sixth byte, usually holds at least the first 3 bytes of the OOB NAND Flash hardware ECC code.

ECC typically generates 3 bytes of ECC checksum data per 256 bytes of raw data, and the 24-bit checksum data is divided into 6-bit column checksum data and 16-bit row checksum data, with the remaining 2 bits set to 1, as follows:

ECC row check generation rules as follows, and Hamming code similar to the idea:

Where the row validation generation rule is:

P8 = bit7 (+) Bit6 (+) bit5 (+) BIT4 (+) bit3 (+) Bit2 (+) bit1 (+) Bit0 The result of an XOR operation on all bits of all even row bytes.

P8 ' = bit7 (+) Bit6 (+) bit5 (+) BIT4 (+) bit3 (+) Bit2 (+) bit1 (+) Bit0 The result of an XOR operation on all bits of all odd-numbered rows of bytes.

Column check generation rule:

P1=d7 (+) D5 (+) D3 (+) D1 P1 ' =d6 (+) D4 (+) D2 (+) D0

P2=d7 (+) D6 (+) D3 (+) D2 P2 ' =d5 (+) D4 (+) D1 (+) D0

P4=d7 (+) D6 (+) D5 (+) D4 P4 ' =d3 (+) D2 (+) D1 (+) D0

This d6,d4 is the bit value for all the bytes on the save. For example, P4 is the result of an XOR operation for BITS 4 5 6 7 of all bytes. P2 is the result of an XOR operation of Bit2 3 6 7 for all bytes.

Based on the above calculation results, the ECC three-byte saving layout is summarized:

When writing data to NAND flash page, we generate an ECC checksum per 256 bytes, called the original ECC checksum, saved to the page's OOB (out-of-band) data area.
When reading data from NAND flash, we generate an ECC checksum per 256 bytes, called the new ECC checksum.
Verification, according to the above ECC generation principle is not difficult to infer: will read from the OOB area of the original ECC checksum new ECC checksum and the bitwise XOR, if the result is 0, it means that there is no error (or the ECC can not detect errors), if 3 bytes xor The result of 11 bits is 1, Indicates that there is a bit error and can be corrected; if there are only 1 bits of 1 in the 3 byte XOR result, there is an error in the OOB area, and all other cases indicate uncorrectable errors.

Reference documents:

http://blog.csdn.net/noodies/article/details/4335320

http://czhjchina.blog.163.com/blog/static/20027904720126203271790/

http://blog.csdn.net/nhczp/article/details/1700031

Technorati Tags: Nand Flash ECC

ECC calibration principle and its application in NAND flash