FPGA chip Internal Hardware introduction

FPGA chip Internal Hardware introduction

FPGA (Filed programmable gate Device): Field programmable logic device

???? FPGA based on the structure of the lookup table plus trigger, using the SRAM process, but also using flash or anti-fuse technology, the main application of high-speed, high-density digital circuit design.

???? FPGA consists of programmable input/output unit, basic programmable logic unit, embedded block RAM, Rich cabling resources (clock/long line/short line), bottom embedded function unit, embedded dedicated hard core, etc.

???? The most widely used FPGA chip in the market is from Altera and Xilinx. In addition there are some other manufacturers of low-end chips (Actel, Lattice).

This article mainly introduces the internal hardware structure of the AlteraCyclone II series FPGA:

1. FPGA device Structure
2. Programmable input/output unit IoE
3. Programmable Logic Unit Le
4. Embedded Block RAM
5. Cabling Resources
6. Bottom embedded function unit

FPGA device Structure

Altera Cyclone IV Device structure

The internal structure of the FPGA includes:

1. Programmable logic Gate array consisting of the smallest unit Le
2. Programmable input/output unit IoE
3. Embedded Ram block, m4k block, each storage capacity is 4K, lost power loss
4. Cabling Network
5. PLL phase-locked loop, ep4ce6e22c8n maximum octave to 250MHz, which is the maximum operating frequency of the chip

Programmable input/output unit IoE

Programmable I/O, configurable as OC Gate, Tri-State Gate, bidirectional io, single-ended/differential, etc. support a variety of different I/O standards: LVTTL, Lvcoms, SSTL, LVDS, Hstl, PCI, etc.;

Altera Device IOE Structure

Altera device input and output structure: configurable as tri-state, input/output, bidirectional IO

The IOE structure in the Cyclone series in Altera devices is the basic input, output, and enable trigger structure.

Programmable Logic Unit Le

The basic programmable logic unit Le consists of a lookup table (look up table) trigger (FF), and Le is the smallest unit that makes up the lab;

The LUT is typically a 4 input lookup table, the high-end device (Xilinx V5) uses the LUT-6 structure, and the Lut can be seen as the RAM structure of the 16x1 of the 4-bit address line.

FF is a programmable trigger that can be configured as a synchronous/asynchronous reset, synchronous/asynchronous set-up, enable, load and other function triggers.

Programmable logic blocks:

Altera:lab

Xilinx:clb

Xilinx CLB consists of four slice, while Altera's lab is comprised of 16/8 le;

Basic Logic Unit Le/slice:

Altera:le

Xilinx:slice

Xilinx for Slice: Includes two lut-4/two FF;

Altera for Le: includes a lut-4/one FF;

Embedded Block RAM

Embedded block RAM can be configured with single/dual-port RAM, pseudo-dual-port RAM, ROM, FIFO, SHIFT, Cam, etc. the block RAM sizes vary by manufacturer:

???? altera:m512, m4k m4k, M-ram (512K);

???? Xilinx:18kbit;

???? Lattic:9kbit;

?

ALTERA:M4K:

Cabling Resources

Global cabling resources: For global clock/Global reset/Global position routing;

???? Long-term resources: for the bank or embedded function unit of high-speed signal or the second global clock cabling;

???? Short-term resources: for the logical interconnection between the logical units and cabling;

Global Cabling Resources:

Global Clock Tree:

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Underlying embedded function block

Mainly refers to PLL/DPLL, DCM, DSP48, multiplier, embedded hard core/soft core;

???? XILINX:DCM, dsp48/48e, DPLL, MultiplieR, etc.

ALTERA:PLL/EPLL/FPLL, Dspcore, etc.;

Multiplier structure

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PLL/DCM: Embedded Phase-locked loop

Altera:pll

Xilinx:dcm

Altera's Cyclone II device has a maximum of four plls, distributed at Four corners of the chip, and the main thing is that the Altera PLL is an analog phase-locked loop, which needs to be considered in terms of power/ground.

Xilinx's spatan-3 devices have a maximum of four DCM, and are also distributed on the four corners of the chip.

the difference between the two: Altera's PLL can support a lower input frequency, while Xilinx's DCM supports a minimum phase-locked frequency of 24/32mhz, but Xilinx's high-end device Virtex-5 DPLL can achieve very low input frequencies.

Embedded dedicated Hard Core

Refers to high-speed serial transceiver; GMAC, SERDES, PCIe, etc.;

Xilinx:gmac, SERDES, PCI, GTX, GRX

Atera:gmac, SERDES, PCIe, SPI.4/SFI.5

FPGA chip Internal Hardware introduction