FPGA low temperature cannot start analysis

FPGA low temperature cannot start analysis

Phenomenon Description: In the medium plate light end machine to do low-temperature test, respectively to the transmission version, the receiving board power-off restart, found that some boards in the -40° can start, and some boards in -20° are not able to start, need to raise the temperature to 0° above to start, The observed phenomenon is that the 4 LED lights that indicate the status are lit, and the FPGA is always in reset mode.

In response to this problem, the following analysis is made:

FPGA before power up is a blank chip, even before the power off the FPGA has been configured as a normal working system, but as long as the power outage, it resumed the blank. That is to say, the circuit logic inside the FPGA should be implemented to a specific structure need to have electricity maintenance.

The internal logical structure of the FPGA is determined by the configuration file, which depends on the configuration mode used by the FPGA. Medium optical End Machine FPGA is the main string mode, which is the most commonly used in FPGA configuration mode, the main string configuration mode circuit is as follows.

The FPGA chip used by medium optical end machine is Spartan3e,platformflash is xcf04s.

The FPGA chip has two configuration trigger events: Power-on Reset (POR), software reset. In the low temperature test, we use the method of power-off restart to detect whether the FPGA can be restarted at low temperature, here mainly to the power-on reset trigger reconfiguration process is described as follows:

(1) FPGA power on, only in the core voltage, reference voltage, IO port voltage is normal, only enter the configuration mode;

(2) drop-down PROG_B,FPGA reset, while the Configuration storage space is initialized;

(3) The Init_b,done PIN signal is pulled low, the done signal is connected with the CE pin signal of prom chip, so that the prom chip selection signal is effective; the init_b is low, indicates the power supply voltage is normal, the FPGA is in the Configuration Storage space initialization;

(4) FPGA in the Prog_b pin signal becomes high, start the configuration process;

(5) The FPGA reads the value of the configuration pin m[2:0] in the Init_b rising edge, thus determining the configuration mode of the FPGA;

(6) Prom passes the configuration data to the FPGA at the rate of the CCLK clock signal via the Do pin

(7) After the configuration is complete, set the done pin signal low to indicate that the configuration is complete.

The following is an analysis of several key factors in the FPGA Main-string mode configuration process:

1. por Voltage requirements

During power-on reset, the Por circuit will remain in the reset state if the supply voltage is not configured to reach the threshold value. There are three configurations of power supply:

Vcciint, the logic of the FPGA core voltage supply;

Vccaux, give the special configuration pin for pressure;

Vocc_2, for externally connected configuration data sources (such as prom) interface pin pressure

FPGA detects these three voltage values, once all three voltage values exceed the specified voltage threshold, the Por power-on reset circuit releases the reset control, and the FPGA can start reconfiguring at low Prog_b.

Por reset voltage threshold value Table

2, configuration mode selection: Main string mode (Master Serial)

m[2:0]= <0:0:0>,FPGA configuration Mode Select Pin m[2:0] should be low. After the FPGA has completed the internal Configuration Storage space initialization, Fpgat_b reads the level value of the configuration mode pin at the Init_b rising edge, thus determining the configuration mode of the FPGA.

==> Check M0 M1 M2 on the pull-down resistor, these feet FPGA built-in pull is strong, if the external pull-down resistor is too large, it is possible that the drop-down level is not low enough, coupled with temperature changes in the input threshold voltage changes may cause low temperature when not to use SPI Flash initialization. Recommended resistance 470 Euro below, if the pin is not used, it is recommended to ground directly.

3. Configuring the Clock CCLK

CCLK signal is the clock signal of JATG configuration data transmission, its signal integrity is very critical. The CCLK is generated by an internal FPGA oscillator and passed to the CLK pin of the platform Flash Prom. Accordingly, the Platformflash prom sends the configuration data to the FPGA through do at a rate of CCLK. If the CCLK signal is not available, focus on checking the kernel for 1.2v. The FPGA configuration circuit has just begun to work at the lowest frequency, and if not specifically specified, will gradually increase the frequency. For different chips and levels, the CCLK maximum value is as follows.

4. PROG_B-FPGA Reset or reconfigure

Prog_b is an asynchronous control input signal to the FPGA, when the Prog_b is low, the FPGA resets, and the Configuration Storage space is initialized, and when the prog_b from low to high, the FPGA begins the reconfiguration process; When the reconfiguration is complete, the Prog_b remains high, Once the Prog_b has a falling edge and the low-level duration is greater than 500ns, the FPGA begins the reconfiguration process.

Prog_b is the low period, the IO pin will show what state it is. In the case where the hswap is low, the enable pull-up resistor, once detected a falling edge of the Prog_b, the IO pin of the FPGA will be invalid and be pull to a high level. If the Hswap is high, the pull-up resistor is not valid and the status of the IO pin of the FPGA is indeterminate.

==>medium Optical End machine, hswap through a 510 ohm resistor grounded, so hswap is low, when the Prog_b is low, the IO pin of the FPGA will be pull high, this time indicates the status of four LED lights just explain this phenomenon.

5. INIT_B-FPGA Configuration Storage space initialization indication signal

When the power supply voltage reaches the threshold value, the Fgpa init_b to low, indicating that the Configuration storage space is being initialized. When the init_b signal is changed from low to high, the FPGA reads the level value of the configuration mode pin m[2:0] To determine the configuration mode of the FPGA.

During configuration, the FPGA indicates a configuration data error, such as a CRC error, by placing the init_b low.

DONE-FPGA Configuration status Indication signal

Done is low when the FPGA is in the configuration process, and becomes high when the configuration is complete. Can be used to indicate the configuration status of the FPGA.

The done pin of the FPGA in the ==>medium optical end machine is connected with an external 240 ohm resistor (330 ohms recommended), and an LED is connected outside the other end, and then grounded. When the LED is lit, the FPGA has been configured.

6, Summary:

Through the above analysis, when the FPGA is not properly configured, you can troubleshoot from the following aspects:

1. Done indicates whether the signal led is on or off and the configuration is complete;

2. The measured voltage is normal, the core voltage (1.2V), the reference voltage (2.5v), the IO port voltage (3.3v), respectively;

3. Check the configuration mode m[2:0] is correct, (m[2:0]=<0:0:0>);

4. Use oscilloscope acquisition to configure the clock signal to see if it is normal, less than 12M (Spartan 3e + xcf04s)

5. The data sheet of the PROM, prom--xcf04s can work in -40° to +85° environments.

7. Reference documents:

1.ds312-spartan-3e FPGA Family Data sheet.pdf

2.ug332-spartan-3 Generation Configuration User guide.pdf

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Shanekong
Source: CSDN
Original: 29923925?utm_source=copy
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FPGA low temperature cannot start analysis (RPM)