FPGA Power Consumption Structure Design

1 compared with ASIC, FPGA is a power-consuming device and is not suitable for designing ultra-low power consumption.

2 in CMOS technology, the dynamic power consumption of the circuit is related to the charge and discharge of the gate and the metal lead. The general equation of capacitor current consumption is

I = V * C * F

V is the voltage, which is a fixed value for FPGA. The C capacitor is related to the number of directly triggered doors and the wiring length of these doors. The frequency f is directly related to the clock frequency. Therefore, reducing power consumption must begin with reducing C and F.

A clock-selecting is a direct method to reduce dynamic power consumption, but it may cause difficulties in timing analysis. The clock enabling trigger input or the global clock multiplexing selector should be used instead of the direct clock selection. Selecting a clock in an FPGA will bring about a new clock domain, causing a conflict, and these may not be optimized by the compilation tool. As shown in:

If the value of DL <DG is greater than the value of DL, the retention time is incorrect.

B. Minimizing the rising and falling edges of the drive signal can reduce the power consumption of the input device.

C. Do not leave the FPGA input buffer blank. (The suspended pin is regarded as the input of the variable slowly)

D. The dynamic power consumption is proportional to the square of the voltage, so we can reduce the FPGA power supply voltage and reduce the power consumption,

E dual-edge triggering can reduce the frequency and reduce the power consumption (however, only corresponding devices are required)

F uses serial interfaces without the consumption of steady-state current.