FPGA timing constraints (Altera timequest)

A good timing constraint can be used to guide the layout and wiring tools to weigh and obtain the optimal device performance, so that the design code can reflect the designer's design intent to the greatest extent possible.

2 timequest is an ASIC-style static timing analysis (STA) tool added by Altera to the 6.0 software. The Synopsys Design constraints (SDC) file format is used as the time series constraint input.

3. timequest checks the creation time and retention time. Asynchronous signals are the recovery time and removal time. There are also multiple cycle constraints.

4. The purpose of the time series check is to confirm that the signal hop occurs in the "signal hop arrival window" instead of the "signal level Sampling window.

5. Sample Code 4 of the sub-device. Note the comment "synthesis keep" in the code, which is inserted into the code to command the Quartus II software to retain the specified node and the name of the node in the final circuit implementation. This allows us to use reserved nodes as a reference.

Figure 4 example of the sub-generator's OpenGL code