FPGA timing problems and fpga timing problems

FPGA timing problems and fpga timing problems

Recently I made a project ------ 4 1080 p (1920x1080) to synthesize a 4 K (3840x2160,297 M) interface board. When 1080 p goes in and p goes out, the video is played normally. However, when P and 4 K are in progress, the video image will have water ripple. At that time, it was assumed that the timing sequence sent by FPGA to the downstream device SII9136 could not be met. As a result, the output clock is reversed to a certain extent, and the water ripple is much less. After I used the oscilloscope, I found that the timing sequence was missing. Then two reverse operations are added. Oh, God. It's successful! Sprinkling flowers ......

 assign IDCK_OUT = ~clk_out_test1;  assign clk_out_test = ~clk_rd;  assign clk_out_test1 = ~clk_out_test;  //assign D_OUT[35: 28] =      //    always @(posedge clk_rd or negedge global_reset_n)    begin      if (~global_reset_n)         begin           D_OUT[31: 0] <= 32'b0;//   D_OUT[25: 0]  <= 26'b0;         end      else        begin          D_OUT[31: 24] <= dout_c[7: 0];      //  DD35  ------DD28                 D_OUT[19: 12] <= dout_c[15: 8];     /// DD23 -----DD16       //   D_OUT[26:24] <= 3'b0;      //    D_OUT[15: 0] <= 16'b0;          //   D_OUT[34: 27] <= dout_c[7: 0];          //   D_OUT[23: 16] <= dout_c[15: 8];        end    end

Conclusion: Generally, when the timing of FPGA-> downstream devices is insufficient, reverse or PLL migration can solve the problem.

FPGA timing problem: What clock frequency does the Code executed in sequence between begin end run ?? Or other time series methods?

First, FPGA code is integrated into a circuit instead of being executed. begin end is a small circuit module. Therefore, the relationship between them and the clock should be analyzed in detail.
The first is the type of the variable you define. Among the two common types, register reg and linear wire, only register may have a delay in the clock cycle. The effect is similar to D Trigger.
Next, the most important thing is that the order of values assigned to several register variables between the begin-end module depends on the blocking type assignment or non-blocking type assignment. For blocking assignment, use "="; for non-blocking assignment, use "<= ".
As the name implies, the non-blocking value assignment statement is that each reg variable has no successive relationship. When the clock trigger condition of the begin end module is met, each reg variable is assigned and operated simultaneously; the blocking value assignment statement assigns values to different register value assignment statements according to the code sequence. The value assignment of the reg variable will delay a clock period from the previous line.
Finally, it is worth noting that the same begin end module cannot be mixed with two assignment statements. In general, the time series circuit always block uses non-blocking assignment "<= ", when combining the logic always block and assign statements, assign a blocking value "= ".

FPGA timing constraints

Pad to Setup refers to the sum of Input Pad Delay Time and Fist FlipFlop Setup Time

Clock to Pad refers to the sum of the last-level register data creation time and output pin Delay Time