FPGA training expert V3 College FPGA expert takes you to learn Verilog language Top_down writing skills

This article is originally from V3 College Www.v3edu.org,FPGA training Specialist

In order to improve the reuse rate of our code, we can write the code of different functions and then connect to the top layer. We give a simple example, the following procedure, we implement the LED water.

In the LED module, we first divide the system clock into 1HZ clock, and then use the crossover clock to control the flow of LED lights, but my crossover and led light flow is not the same project, just put the frequency after the clock as the LED light control clock. In this way we will find that if I use the module of the running lights again, I need to modify a lot of places, so in order to make our module reuse rate is higher, more easy to reuse, we can sub-module writing, and then on the top layer to connect. The following is the program that we have written in the module.

Divider module:

LED Light Flow module:

Top-level modules:

Our integrated circuit diagram is:

Through the Top_down writing, our module of the reuse rate will be greatly improved, when we use the next time the LED light flow or crossover module when the module directly copied the past connection.

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This article is originally from V3 College Www.v3edu.org,FPGA training Specialist

FPGA training expert V3 College FPGA expert takes you to learn Verilog language Top_down writing skills