Configapplication_allocated_heap defined as 1 requires the user to heap their own memory ucheap, otherwise
is the compiler to assign.
Heap_4.c
Configassert (x)
Xtaskcreatestatic ()
Configcheck_for_stack_overflow
Configgenerate_run_time_stats
Set to 1 Turn on time statistics function
When the Configidle_should_yield is 1, the idle task will yield the user task at the same priority level.
CPU usage.
Configmax_co_toutine_priorities
Configmax_priorities
Configmax_task_name_len
Configminimal_stack_size
Configqueue_tegistry_size
Configtick_rate_hz
Configtimer_task_priority
Xreturn = Xtimercreatetimertask (); How this task is applied ...
Configuse_16_bit_ticks
For 1, the ticktype_t is 16 bits, and 0 ticktype_t is 32 bits.
Configuse_counting_semaphores
When set to 1, the count semaphore is enabled and the associated API functions are compiled.
Configuse_idle_hook
Configuse_mutexes
Configuse_port_optimised_task_selection
Configuse_preemption
Use the preemption Scheduler at 1, and use the co-process for 0.
Configuse_queue_sets
Configuse_task_notifications
When you use the task Notification feature for 1, each task consumes 8 more bytes when this feature is turned on.
What's the difference between opening and not opening ....
Configuse_tickless_idle
For 1 o'clock enable low power tickless mode. How to turn on low power is how to run ...
Configuse_timers
Use a software timer for 1. When to turn on the software timer ...
Configuse_time_slicing
Tasks with the same priority as 1 o'clock are toggled in a clock-beat interrupt, 0 o'clock, and do not break at clock ticks
Task switching for the same priority task:
The CORTEX-M core MCU provides a nested vector interrupt Controller (NVIC) for interrupt management.
COTEX-M3 and M4 's Nvic support up to 240 IRQ (interrupt request), one non-shielded interrupt (NMI), 1 Systick
(tick timer) timer interrupt and multiple system exceptions.
Three interrupt screen registers: Primask, Faultmask, and Basepri.
The STM32 has a level 16 priority.
To make the preemption function more controllable, the Cortex-m processor also divides 256 priority bits into high and low ends:
Preemption Priority (Group priority) and sub-priority (sub-priority), a register in Nvic is
"Application interrupt and reset control register (AIRCR)", the AIRCR register has a single-digit segment named "Priority Group".
[10:8] Prigroup priority grouping
The STM32 uses 4-bit, so there are up to 5 groups of priority grouping settings.
Nvic_prioritygroup_4
If you choose Nvic_prioritygroup_4, then the 4-bit priority is all preemption priority, no sub-priority
, then there are 0-15 total of 16 priority levels.
Pri_12 0XE000_ED20 The priority of the debug monitor
... 0xe000_ed21 ...
Because FreeRTOS is a direct-action address when setting the interrupt priority for PENDSV and Systick 0XE000_ED20
Special registers for interrupt masking
Primask and Faultmask Registers
In many applications, it is necessary to temporarily block all interrupts to perform some of the tasks that are strictly required for timing, which can
Using the Primask register, Primask is used to prohibit all exceptions and interrupts except NMI and Hardfault,
Cpsie I; Clear Primask (Enable interrupt)
Cpsid I; Set Primask (disable interrupts)
The Primask register can also be accessed through the Mrs and MSR directives, as follows:
MOVS R0, #1
MSR Primask, R0;
Faultmask than Primask more ruthless, it can even hardfault shield off, Faultmask will automatically clear when exiting.
BASEPRI Register
The shielding priority is no higher than the 0x60 interrupt,
MOV R0, #0X60
MSR Basepri, R0
Unblock basepri against interrupts
MOV R0, #0
MSR Basepri, R0
Attention. The FreeRTOS switch interrupt is the operation of the BASEPRI register to achieve. It can turn off interrupts below a certain threshold.
, interrupts above this threshold will not be closed.
Configprio_bits
This macro is used to set the MCU to use several priority levels, STM32 uses 4 bits, so this macro is 4
Configlibrary_lowest_interrupt_priority
This macro is used to set the lowest priority level
Configkernel_interrupt_priority
This macro is used to set the kernel interrupt priority.
Portnvic_syspri2_reg
Configlibrary_max_syscall_interrupt_priority
This macro is used to set the maximum priority that the FreeRTOS system can manage, and the BASEPRI register says that threshold priority, where
The priority set to 5, which is higher than 5, is not managed by FreeRTOS.
FreeRTOS switch Interrupt function for portenable_interrupts () and portdisable_interrupts ()
Freetros has 4 functions related to critical section Code protection: taskenter_critical (), taskexit_critical (),
Critical segment code protection at the task level
TASKENTER_CRITICAL_FROM_ISR () and TASKEXIT_CRITICAL_FROM_ISR ()
Critical code protection for interrupt levels
Note that the critical section code must be streamlined, because entering the critical section closes the interrupt, which causes the priority to be lower than the configmax_syscall_interrupt_priority
Interruptions do not get a timely response.
Interrupt level critical Segment code protection
TASKENTER_CRITICAL_FROM_ISR () and TASKEXIT_CRITICAL_FROM_ISR ()
is used in the Interrupt service program, and the priority of this interrupt must be lower than configmax_syscall_interrupt_priority
Task functions are generally not allowed to jump out of the loop, if you must jump out of the loop after jumping out of the loop must call the function Vtaskdelete (NULL) Delete this task.
Task Control block
typedef TSKTCB TCB_T;
Sixth Chapter FreeRTOS task-related API functions
Xtaskcreate () Create a task using a dynamic method
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