GUN make study notes in linux (1) and gun Study Notes

GUN make study notes in linux (1) and gun Study Notes

Chapter 1: Overview

1.1: make Overview

In a linux environment, you can easily build your own project using the make tool. The compilation of the entire project requires only one command to complete the compilation, connection, and final execution. However, we need to spend some time learning how to compile the makefile file, which is also the basis for the normal operation of make.

The makefile file describes the compilation and connection rules of the entire project. These include: Which source files in the project need to be compiled, how to compile, how to create those library files, how to create these library files, and how to finally generate the executable files we want.

Make is a command tool that explains the commands in makefile. The makefile file describes the compilation sequence and rules of all files in the project. Makefile has its own writing format, keywords, and functions. The C language has its own format, keyword, and function. In makefile, you can use any command provided by the system shell to complete the desired work.

1.2: Preparation

Before discussing make, you need to clarify some basic concepts:

Compile: convert code written in advanced languages into machine-identifiable machine commands. The compiled machine commands can be recognized by machines but cannot be executed. During compilation, the compiler checks whether the syntax, functions, and variables of advanced languages are declared correctly. The compiler can compile the intermediate target file only when all syntaxes and related variables are correctly defined. Generally, a source file in a high-level language can correspond to a target file. The default Suffix of the target file in linux is ". o ".

Link: links to multiple target files or target files and library files are called executable programs that can be executed by the operating system. The linker does not check the source file where the function is located, but only checks the defined symbols of all target files. Merge the functions used in the target file with the related symbols in other target or library files, reschedule the symbols in all files, and connect the system-related files to generate executable programs.

Static Library: a set of more than 10 target files, also known as document files.

Shared Library: it is also a collection of multiple target files, but these target files are generated in a special way. The addresses of each member in the module are relative addresses. When a program using this shared library is running, the shared library is dynamically loaded into the memory and linked to the main program in the memory. Multiple executable programs can share code segments in the library file.

　　

Chapter 2: Introduction to GUN make

Makemakefile tells make how to compile and link programs. When a file is updated, make compares the last modification time of the corresponding file to determine which files need to be updated, run the command on the required file.

2.1: makefile introduction:

When you use the make tool for compilation, some files in the project will be compiled when you execute make:

1. If no source file has been compiled, compile and link each c source file to generate the final executable program;

2. Each c source code file modified after the last make execution will be re-compiled during the current make execution;

3. the header file was modified after the last make operation. All the c source files containing this header file will be re-compiled when you execute make.

2.2: Introduction to makefile rules:

A simple makefile description rule consists of the following:

TARGET...: PREREQUITES

COMMAND

Target: the target of the rule, usually the final file name to be generated or the intermediate process file name required to achieve this goal. It can be the target file or the final executable program file name. In addition, the target can also contain the name of the action to be executed by make, such as clean. We call it a pseudo target.

Prerequisites: Rule dependency. Generate a list of file names required by the rule. A file usually depends on one or more files.

Command: the command line of the rule. Is the action to be executed by the rule (any shell command or program that can be executed under the shell ). It limits the actions required by make to execute this rule.

A rule can have multiple command lines, each of which occupies one line. Note: Each command line must start with a [tab] character, and the [tab] character tells make that this line is a command line. Make completes the corresponding action according to the command. This is also an easy-to-use and hidden error in makefile writing.

A command is the Action Description of recreating a target after the dependent file of any target changes. A target can have no dependencies but only actions.

The rules in makefile are used to describe under what circumstances and how to recreate the target file of the rule. Generally, the rules include the dependency of the target and the commands for recreating the target. Make: Execute the command to recreate the target to create or recreate the target. The rule contains the dependency between files and the commands required to update the rule target.

The make program depends on the Rule dependency and determines that the execution rule is sufficient for executing the command defined by the rule.

2.3: simple example

Main. c:

#include"hello.h"int main(){    print();    return 0;}

 

Hello. c:

#include"hello.h"void print(){    printf("hello world!\n");    }

Hello. h:

#ifndef HELLO_H#define HELLO_H#include<stdio.h>void print();#endif

 

The makefile file is as follows:

obj = main.o \
　　hello.omain: $(obj)gcc $(obj) -o mainmain.o: main.c hello.hgcc -c main.c -o main.ohello.o: hello.c hello.hgcc -c hello.c -o hello.oclean:rm -rf *.o main

　　

When writing, you can use a backslash to break down a long row into multiple rows, making it easier to understand. However, note that there cannot be spaces after the backslash. After this makefile is complete, you need to create the executable program main. All you need to do is to enter the make command in the directory containing this makefile. Delete the files generated by using make in this directory. You only need to enter the make clean command.

The command line must start with the tab key, which is different from other makefile lines. That is to say, all command lines must start with the tab character, but not all lines starting with the tab character are processed as the command line. (Remember: The make program does not care about how the command works. to update the target file, you must provide the correct command in the rule description. What the make program does is execute the command defined by the rule when the target program needs to be updated ).

The target clean is not a file. It only indicates the identity of an action to be executed. Normally, you do not need to execute the action defined by this rule. Therefore, the target clean does not appear in the dependency list of any other rules. Therefore, the action specified by make is not executed. Unless explicitly specified when executing make. In addition, the target clean does not have any dependent files. It has only one purpose: to execute the commands defined by the target name. In makefile, targets that do not have any dependency but execute actions are called pseudo targets.

2.4: How make works

By default, make executes the first rule in makefile. the first goal of this rule is the ultimate goal or the ultimate goal. For example, the main file in the previous example.

After you type the make command in the shell, make reads the makefile file in the current directory, takes the first target in the makefile file as its ultimate goal, and starts to process the first rule. Before processing the commands defined by this rule, you must first update the rules for all dependent files in the target main. There are three situations in which the rules for target files are processed:

1. If the target file does not exist, use its description rules to create it;

2. If the target file exists, any of the. c source files or header files in the target file will be updated later than the target file. Then it is re-compiled according to the rules;

3. the target file exists. The target file is updated with nothing compared to any of its dependent files.

If the target of a rule in makefile is not dependent on the ultimate goal, the rule will not be executed unless it is explicitly specified to execute the rule.

After creating or updating the target file, the make program will process the rule of the ultimate target main in three situations:

1. If the target file does not exist, execute the rules to create the target main;

2. If the target file main exists and one or more dependent files are updated, the mian is relinked according to the rules;

3. the target file exists. It is newer than any of its dependent files, so nothing is done.

To sum up a makefile file, make first resolves the rules for the ultimate goal and searches for the rules for these files based on their dependent files. First, search for the Creation Rules for the first dependent file. If the first dependent file depends on other files, search for the Creation Rules for the dependent file, find the appropriate creation rules for all dependent files. Then make starts execution from the last rule rollback, and finally creates and updates the first dependent file for the ultimate goal. And then to the First, Second, Third ,... The ultimate target depends on the file to execute the same process. The last step is to create the target rule.

In the process of updating the ultimate goal, if any rule has an error, make will immediately report an error and exit. Make is only responsible for executing rules throughout the process, but does not make any judgment on the correctness of the dependencies described by specific rules and the correctness of the commands defined by the rules. That is to say, whether the dependency of a rule is correct and the rule command line that describes the reconstruction target is correct. make does not check any errors. Therefore, it is especially important to write a correct makefile file and love you.

2.5: Set Variables

In the above example, obj is a specified variable, which can be directly used each time. This not only reduces the writing workload, but also reduces the possibility of errors caused by modifications.

2.6: automatically deriving rules

When you use make to compile the. c source file and compile the. c source file, the command for compiling the. c source file rule does not need to be explicitly given. This is because make has a default rule that can automatically compile the. c file and generate the corresponding target file. He runs the command cc-c to compile the. c file. In makefile, we only need to provide the target file name to be rebuilt. meke will automatically find a suitable dependent file for the target file and use the correct command to recreate the target file, for the above example, the default rule is to use the command "cc-c main. c-o main. o "to create the file 'main. o' to a target file. This default rule is called the implicit rule of make.

When writing, we can omit the rules that describe the target file with duplicate names and the dependent file. We only need to describe specific rules. Therefore, the preceding example can be written as follows:

obj = main.o hello.omain: $(obj)        cc -o main $(obj)main.o: hello.hhello.o: hello.hclean:        rm -rf *.o main

　　

2.7: Alternative makefile

We can also group rules based on dependencies rather than targets. The makefile in the previous example can be implemented as follows:

obj = main.o hello.omain : $(obj)        cc -o main $(obj)#(obj) : hello.hclean:        rm -rf *.o main

　　

In this example, hello. h is used as the dependent file for all. o files. However, this writing method is not recommended and it will be troublesome for later maintenance.

The recommended method for writing rules is single-target and multi-dependency. That is to say, try to make sure that only one target file exists in a rule and multiple dependent files may exist. Avoid multiple targets as much as possible.

2.8: Clear the working directory process File

In addition to the source code compilation, the rules can also complete other tasks, such as the rules mentioned earlier to clear temporary files generated during the compilation process.

clean:        rm -rf *.o main

　　

In actual applications, we will write this rule as a little more complex to prevent unexpected situations.

.PHONY:cleanclean:        -rm -rf *.o main

　　

The two implementations have two differences:

1. Declare the clean target as a pseudo target through the ". PHONY" special target. This prevents the command of the rule where the target clean is located from being executed when a clean file exists on the disk.

2. Use-before the command line to ignore the execution error of the command "rm.

Such a goal cannot be the ultimate goal in makefile. Because our original intention is not to execute the delete action after you input make on the command line. Instead, create or update programs.