I2C bus learning-check for missing traps-S3C2440 I2C Controller After learning the theoretical part of the IIC bus protocol, I think we should learn how to operate the 2440 IIC controller. After all, it is all about learning the S3C2440, so I will add this part. The I2C interface of S3C2440 can work in four modes: Host transmitter, host receiver, slave transmitter, and slave receiver. Shows its internal structure. We can see that the S3C2440 provides four registers to complete all IIC operations. The data on the SDA line is sent from the iicds register through the shift register, or transmitted to the iicds register through the shift register. The iicadd register stores the S3C2440 address as the slave address; iiccon and iicstat registers are used to control or identify various States. For example, they select the working mode, send S and P signals, decide whether to send ACK signals, and check whether ack signals are received. The following describes the usage of each register.
Iiccon register IIC-bus control register
Note:
- IIC interruption occurs in the following three situations: when the address information is sent or a slave address is received and matched, when the bus president fails, when one byte of data (including the response bit) is sent/received. an interruption occurs when the address information is sent or a slave address is received and matched, in the interrupt processing function, you must prepare to send or to receive data, that is, to read or send a P signal to the iicds register of the device. an interruption occurs when the bus president fails. In the interrupt processing function, it is decided to compete for the bus again after the delay. Generate an interruption. In the interrupt processing function, prepare to send or receive data next time, that is, read or the iicds register of the device , or send a P signal .
- Based on the online time characteristics of SDA and SCL, when sending data, the data is first written to the iicds register, and then the interruption is cleared.Clear the interrupt, that is, to write 0 to iiccon [4], that is, to pull the SCL line up. At this time, a rising edge is generated, and the data in the shift register is sent to the SDA line. AsWrite the data to the iicds register first, and then clear the interrupt. It may take some time to stabilize the data. InClear the data that needs to be asked before interruption.
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- If iiccon [5] = 0, iiccon [4] will not work properly. Therefore, you must set iiccon [5] to 1 even if you do not use IIC interruption.
Iicstat register Iicadd register
The bit [7:1] that uses the iicadd register, indicating the slave address. The iicadd register can be written only when the serial output enable iicstat [4] is 0. It can be read at any time.If the value of iicstat [4] is 0, the message receiving/sending function is disabled, that is, the check line is lowered.
Iicds registers The bit [] of the iicds register is used, which stores the data to be sent or received. The iicds register can be written only when the Enable iicstat [4] is 1 in the serial output; it can be read at any time.When iicstat [4] is set to 1, the system enables the receiving/sending function, that is, the SCL line is released.
