Intel's past architecture Evolution 5--sandy Bridge

2011 Intel introduced the Sandy Bridge architecture to the Intel processor family Chip (I7,I5,I3) in the second-generation Turadin.

Sandy Bridge was built successfully on the core and Nehalem architecture. It provides the following innovative features:

Intel advanced Vector Extension "Intel Advanced Vector Extensions (Intel AVX)"

-The 256-bit floating-point instruction set expands to 128 for Intel data Streaming SIMD extensions, up to twice times the performance of 128-bit code.

-Non-destructive target coding provides more flexibility in coding techniques.

-Support for flexible migration 256-bit AVX code, 128-bit AVX code and legacy 128-bit SSE code can exist simultaneously

Enhanced front-end and execution engine

-The new decoding cache component increases the bandwidth of the front-end and lowers the penalty for branch prediction failures.

-Advanced Branch Prediction

-Additional macro-fusion support

-A larger dynamic execution window.

-Multi-precision plastic arithmetic enhancement (ADC/SBB, Mul/imul).

-lea bandwidth enhancement.

-reduction of general execution stalls (read port, writeback, write conflict, bypass latency, partial stalls).

-Fast floating-point exception handling.

-xsave/xrstore performance Promotion and xsaveopt new instructions.

Caching architecture provides a wider range of data processing paths

-Doubled bandwidth enhancement through 2 symmetric ports for memory operations

-Fast load and store can be processed simultaneously by adding buffers

-I 2 load and 1 times store internal bandwidth per cycle.

-Improve prefetch performance

-High bandwidth low latency LLC architecture.

-The internal interconnect at the chip level provides a high-bandwidth surround architecture.