LCD Driver debugging log

Mail: bookworepeng@Hotmail.com

Qq: 196568501

Author: DriveMonkey

Undertake various embedded outsourcing projects (fpga, cpld, schematic diagram, pcb, copy board, linux, wince, single chip microcomputer, PC-phone: 13410905075)

Note: the green channel is clk.

The yellow channel is data

Analysis:

1. the LCD parameter is the rising edge of the sent data along the clock descent edge to receive data.

A preliminary analysis of the entire sequence chart is indeed like this. Where is the problem? See Step 2 Analysis

2. Please take a closer look at the figure. The sheup time is 1/2 of the holdup time.

Combined with LCD analysis.

Display symptom: 1) No problem with solid color

2) a problem occurs when a row has two colors.

It is light gray in the upper left corner, dark gray in the upper right corner, and dark gray in the lower right corner.

The light gray in the upper left corner affects the dark gray in the upper right corner.

In the end, the color in the upper right corner and lower right corner is dark gray, but the color in the upper right corner is different from that in the lower right corner.

By comparing the LCD parameters with the signals tested by the oscilloscope, it is found that the setup time is too short.

Solution:

1. Modify setuptime

2. Reduce clock frequency

Both solutions can be implemented.

Because no setuptime can be configured on my LCD controller, I can solve the problem of clock frequency reduction.