Makefile Introduction and how Makefile Works

When the make command executes, a makefile file is required to tell the make command how to compile and link the program.

First, we use an example to illustrate Makefile's writing rules. In order to give everyone a perceptual knowledge. This example comes from the GNU Make manual, in which we have 8 C files, and 3 header files, and we're going to write a makefile to show how the Make command compiles and links the files. Our Rules are:

1) If the project has not been compiled, then all of our C files are compiled and linked.

2) If a few C files of this project are modified, then we only compile the modified C file and link the target program.

3) If the header file for this project is changed, then we need to compile the C file referencing the header files and link the target program.

As long as our makefile is well written and all of this is done with just one make command, the make command automatically and intelligently determines which files need to be recompiled according to the current file modification, compiling the required files and linking the target program.

In the default way, we only enter the Make command. Then,
1.make will find a file named "Makefile" or "Makefile" in the current directory.
2. If found, it will find the first target file in the file (target), in the above example, he will find "edit" This file, and put this file as the final target file.
3. If the edit file does not exist, or edit depends on the file modification time of the. o file is newer than the edit file, then he will execute the command defined later to generate the edit file.
4. If edit depends on the. o file that does not exist, then make will find the dependency of the. o file in the current file, and if found, generates an. o file based on that rule. (This is a bit like a stack of procedures)
5. Of course, your C files and h files are there, so make generates. o files and then uses the. o file to generate the final task of make, which is to execute the file edit.

This is the dependency of the entire make, which makes a layer-by-layer look at the dependencies of the file until the first target file is eventually compiled. In the search process, if there is an error, such as the last dependent file can not be found, then make will directly exit, and error, and for the definition of the command errors, or the compilation is unsuccessful, make does not ignore. Make just file dependencies, that is, if after I find a dependency, the file after the colon is not, then I am sorry, I do not work.

With this analysis, we know that, like clean, which is not directly or indirectly associated with the first target file, the commands defined later will not be automatically executed, but we can explicitly do it. That is, the command-"make clean", which clears all the target files for re-compilation.

So in our programming, if this project has been compiled, when we modify one of the source files, For example FILE.C, according to our dependence, our target FILE.O will be recompiled (that is, in this dependency on the definition of the command), so FILE.O file is also the latest, so FILE.O file modification time than edit to be new, so Edit will also be re-linked (see the commands defined after the edit target file).

And if we change the "command.h", then the KDB.O, COMMAND.O, and FILES.O will be recompiled and the edit will be re-linked.