Makefile Learning (3) [version 2] And makefile learning Version 2

Makefile Learning (3) [version 2] And makefile learning Version 2
Common embedded functions of make

1. function call

$ (Function arguments) # $ the referenced result is the result generated by the function.

 

2. Common functions in Makefile

1) $ (wildcard PATTERN) # match the files in the current directory

For example, src = $ (wildcard *. c) # Matches all. c files in the current directory.

 

2) $ (patsubst PATTERN, REPLACEMENT, TEXT) # pattern replacement function

For example: $ (patsubst %. c, %. o, $ src) # equivalent to $ (src: %. c = %. o) [common]

 

3) execute shell commands in shell functions

Example: $ (shell ls-d */)

 

Multi-level directory Makefile

# Example 1-All compilation is completed by the Makefile in the main directory

CC = gcc

CFLAGS =-Wall-g

 

BIN = main

 

SUBDIR = $ (shell ls-d */) # SUBDIR stores the subdirectories in the current directory

ROOTSRC = $ (wildcard *. c) # ROOTSRC stores the. c file in the current directory.

ROOTOBJ = $ (ROOTSRC: %. c = %. o) # The result of replacing. c In rootsrc with the. o file is saved.

 

SUBSRC = $ (shell find $ (SUBDIR)-name '*. C') # SUBSRC stores all. c files in all subdirectories.

SUBOBJ = $ (SUBSRC: %. c = %. o) # SUBOBJ saves the result after replacing. c with the. o file in SUBSRC.

 

$ (BIN): $ (ROOTOBJ) $ (SUBOBJ)

$ (CC) $ (CFLAGS)-o $ (BIN) $ (ROOTOBJ) $ (SUBOBJ)

 

%. O: %. c

$ (CC) $ (CFLAGS)-c $ <-o $ @ # generate all. c files. o files.

 

Clean:

Rm-f $ (BIN) $ (ROOTOBJ) $ (SUBOBJ)

 

 

# Example 2-each subdirectory has a Makefile file, and each subdirectory is responsible for compiling.

 

DIRS = lib intro sockets advio daemons datafiles db environ \

Fileio filedir ipc1 ipc2 proc pty relation signals standards \

Stdio termios threadctl threads printer exercises

 

All:

For I in $ (DIRS); do \

(Cd $ I & echo "making $ I" & $ (MAKE) | exit 1 ;\

Done

 

Clean:

For I in $ (DIRS); do \

(Cd $ I & echo "cleaning $ I" & $ (MAKE) clean) | exit 1 ;\

Done

 

Generate executable files distributed across multiple directories

# An executable file must be generated for each subdirectory. The structure of the current directory is as follows:

# The content of each file is as follows:

 

//test1/test1.c#include <stdio.h>int main(){    printf("Hello !\n");    return 0;}

# Test1/Makefile

. PHONY: all clean print

 

CC = gcc

CFLAGS =-Wall-g

 

BIN = test1

SOURCES = $ (wildcard *. c)

OBJECTS = $ (SOURCES: %. c = %. o)

 

All: print $ (BIN)

Print:

@ Echo "----- make all in $ (PWD )-----"

 

$ (BIN): $ (OBJECTS)

$ (CC) $ (CFLAGS)-o $ @ $ ^

 

# $ (OBJECTS): $ (SOURCES)

%. O: %. c

$ (CC) $ (CFLAGS)-o $ @-c $ <

 

Clean:

@ Echo "---- make clean in $ (PWD )-----"

-Rm-rf $ (BIN) $ (OBJECTS)

//test2/test2.cpp#include <iostream>using namespace std;int main(void){    cout << "World!" << endl;}

# Test2/Makefile

. PHONY: clean all print

 

CXX = g ++

CPPFLAGS =-Wall-g

 

BIN = test2

SOURCES = $ (wildcard *. cpp)

OBJECTS = $ (SOURCES:. cpp =. o)

 

All: print $ (BIN)

 

Print:

@ Echo "----- make all in $ (PWD )-----"

 

$ (BIN): $ (OBJECTS)

$ (CXX) $ (CPPFLAGS)-o $ @ $ <

 

%. O: %. cpp # The row and the following row can be omitted.

$ (CXX) $ (CPPFLAGS)-o $ @-c $ <

 

Clean:

@ Echo "----- make clean in $ (PWD )-----"

-Rm-rf $ (BIN) $ (OBJECTS)

# Makefile-in the main directory

SUBDIR = $ (shell/bin/ls-d */)

 

. PHONY: default all clean $ (SUBDIR)

 

Default: all

 

All clean:

$ (MAKE) $ (SUBDIR) TARGET =$ @

 

$ (SUBDIR ):

$ (MAKE)-C $ @ $ (TARGET)

# Result after executing make

 

 

# Directory structure after execution

Added a lot of files [. o and executable files]

 

# Execute make clean.

 

 

# Structure chart after execution

Restore original O (recovery _ recovery) O ~

In Linux, there are three makefiles. What do they all do?

By default, make searches for makefile files in the working directory (the directory where make is executed) and reads and executes the files according to the file name order. The file name order is as follows: "GNUmakefile", "makefile", and "Makefile ".
Generally, "makefile" or "Makefile" should be used as the name of a makefile file. (We recommend that you use "Makefile". The first letter is uppercase and the first letter is significant, generally, some important files (such as README and Chagelist) in a directory are close to the current directory, so it is easy to find them ). "GNUmakefile" is a file name that we do not recommend, because only "GNU make" can identify the file named after it, the make program of other versions only contains the files "makefile" and "Makefile" in the working directory.
 
What is the make project manager? How to compile makefile

Copyleft_X answered well. I think this is the case. before writing makefile, I should first find a good makefile and learn about it. Then I am familiar with how makefile works, after a certain degree of conceptual termination, it would be nice to write the makefile thing with me. Remember, never write it very complicated. It would be enough.