Management interface for Mac and PHY connection Mdio

MII Management interface for Mac layer or other control chip (not necessarily the MAC layer chip, possibly MCU, such as high-pass chip construction, 1 MAC chips can control 2 PHY chip, then MCU Control 3 network card (mac+2phy) chip) control, Configure the PHY layer chip.

Through MII Management Interface It is possible to control and configure multiple PHY devices, get status and Err or infomation, and determine the type and capabilities of the attached PHY device (s).

The Mdio interface consists of two signal lines: MDC and Mdio, through which the MAC layer chip (or other control chip) can access the registers of the physical layer chip and use these registers to control and manage the physical layer chip. The Mdio management interface is as follows:
MDC: The management interface of the clock, it is a non-periodic signal, the minimum period of the signal (the sum of the actual positive and negative flat time) is 400ns, the minimum positive and negative flat time is 160ns, the largest positive and negative electric normal between the unrestricted. It has nothing to do with TX_CLK and RX_CLK.
The Mdio is a bidirectional data line that transmits control information and physical layer status information for the MAC layer. The Mdio data is synchronized with the MDC clock and is valid on the MDC rising edge. The data frame structure of the Mdio management interface is as follows:

Figure Mdio The data frame structure of the management interface

In Read/write operation, the management data frame was 64-bits long and starts with the contiguous logic one bits  (p reamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a <01> pattern followed by the operation Code (OP): <10> ; Indicates read operation and <01> indicates Write operation. for read Operation, a 2-bit turnaround (TA) filing between Register Address field and Data field is provided for  mdio to avoid contention. Following the turnaround time, 16-bit data is read from or written onto management  registers.

The meaning of the frame structure fields is as follows:
PRE: Frame prefix domain, 32 consecutive "1" bits, this frame prefix domain is not necessary, some physical layer chip Mdio operation does not have this domain.
ST: The frame start flag, the "01" bit indicates that the frame design begins.
OP: Frame opcode, bit "10" indicates that this frame is a read operation frame, and bit "01" indicates that this frame is a write operation frame.
Phyad: The address of the physical layer chip, 5 bits, each chip has its own address compared to the 5 bits, if the match response to the subsequent operation, if not match, then ignore the subsequent operation.
Regad: The address of a register in the 32 registers used to select a physical layer chip.
TA: State conversion domain, if it is read operation, then the first bit when the mdio is high impedance state, the second bit by the physical layer chip to make Mdio "0". For write operations, the Mdio is still controlled by the MAC layer chip, which outputs "10" two bits in a row.
Data: The domain of the register of the frame, 16 bits, if read operation, the physical layer to the MAC layer of data, if the write operation, the MAC layer is sent to the physical layer of data.
Idle : After the end of the Free State, at this time Mdio passive drive, high-impedance state , but the general use of the pull-up resistor to make it at a higher level, that is, the mdio pin requires a pull-up resistor.

Note: The above images and English are from the "DM9161A data Sheet"

Management interface for Mac and PHY connection Mdio