Microprocessor-operated bus

1. The CPU performs an access to the external memory or I/O interface through Biu, which is called the CPU to perform a bus operation, according to a certain timing relationship. The cycle of performing a bus operation is called a bus cycle. In microcomputer system, the information interaction between CPU and other parts of the system is realized by various types of bus operation. The timing of bus operation constitutes the basic timing relation of microcomputer operation.

2. System Reset and start-up operation

The reset and start-up operation of the system resets the 8086 by applying an effective level to the reset signal. The reset signal requires a high level of 4 clock cycles. Removal of the reset signal, that is, the reset from high to low, the system began to start.
In the reset state, the internal registers of the CPU are set to the following values:
Flag Register Zeroing
CS Register FFFFH
DS Register 0000H
SS Register 0000H
ES Register 0000H
instruction Pointer (IP) 0000H
Command Queue empty
Other registers 0000H
After the CPU is started, the command is taken from the ffff0h address and execution refers to the

When the system resets, the code segment Register CS and the instruction pointer IP are initialized to FFFFH and 0000H, respectively. So after resetting the CPU executes the instruction from the memory of the ffff0h unit. In general, an unconditional transfer instruction is stored at the ffff0h and transferred to the entry of the System program. This way, once the system is started, it automatically enters the system program.
The masked interrupt intr cannot be responded to because the flag register is zeroed when reset.

3. Operation Timing of the bus

According to the direction of data transmission, bus operation can be divided into bus read operation and bus write operation. Bus read operation means that the CPU reads data from memory or I/O port, including fetch, memory read, I/O read, interrupt answer operation can also be regarded as special bus read operation; A bus write is a CPU that writes data to a memory or I/O port, including memory write, I/O write

T1 Status
Starting with the T1 state, the m/io# signal is valid, indicating whether the CPU is going to be memory access or I/O access.
The T1 state is the address state, and the processor issues the address of the memory or I/O port to be accessed. The CPU sends out a high 4-bit address via the address/status line A19/S6~A16/S3, ad15~ad0 the low 16-bit address via the address/data line. Since 8086 of the 20-bit address lines are multiplexed with the state and the data line, the address signal must be locked up in the T1 state. In the T1 state, the address latch of the CPU enables the ALE signal to be valid, and the ale is a forward pulse, which is used for the falling edge of the address latch 8282,ale to have the address signal lock present in 8282. High-level data bus enable signal bhe# is also a time-sharing signal, in the T1 state is sent through the BHE#/S7 pin, bhe# signal as the choice of odd address storage. Typically bhe# and 20-bit address signals are latched with an address latch to make their status valid throughout the bus cycle.
In addition, the data transmission direction control signal of the data bus transceiver dt/r# will also be valid in the T1 state, because this bus cycle is read cycle, the dt/r# output low level, control data bus transceiver to receive.

T2 Status
In the T2 state, the address signal ends, the ad15~ad0 enters a high impedance state, prepares for reading the data, and the output status information s7~s3 on A19/S7~A16/S3 and BHE#/S7.
The CPU output read signal rd#,rd# signal is sent to all the memory and I/O interface chip in the system, together with the address line, open the selected address of the storage unit or the I/O port of the tri-State gate, the data from the storage unit or I/O ports read out, sent to the system's data bus.
At the same time, the data enable signal den# to low level, control bus transceiver into a valid state.

　 T3 Status
The basic bus cycle is a bus cycle that does not have to be plugged into a waiting state, consisting of 4 T states. In the basic bus cycle, the CPU typically latches the data that appears on the data line at the falling edge of the T3.
　 T4 Status
T4 state is the end state of the bus cycle, in addition to the CPU read and write data, m/io#, address and data are all turned into a high-impedance state, ending the current bus cycle.