MIPS architecture analysis, programming and practices [1]

Http://blogold.chinaunix.net/u1/40363/showart_434186.htmlchapter I MIPS CPU Architecture Overview
Chen Huai Lin

1. Preface

This article introduces the MIPS architecture, focusing on its register conventions, MMU and storage management, exception and interrupt handling, and so on.

Through this article, we hope to provide a basic concept of contour for readers who are interested in mips cpu and operating systems.

You can start to read more detailed contract information.

MIPS was one of the oldest and most successful of the large-scale Instruction Set Computer processors and originated from the electrical system of Stanford Univ. Its founder, John L. Hennessy, was founded in Silicon Valley in 1984.
Company (www.mips.com ). John L. Hennessy is currently the principal of Stanford Univ. Prior to that, he was Dean of Stanford Institute of Electronic Engineering. Students Majoring in CS all know two famous books:
"Computer Organization and Design: The Hardware/Software Interface" and
"Computer Architecture: A Quantitative Approach". Its Co-author is Hennessy.

MIPS is abbreviated as "Microcomputer without interlocked pipeline stages. Another common informal statement is "Millions of instructions per second ".

MIPS chips are widely used in the industry: mips inc. R10000; QED (http://www.qedinc.com. From mips inc in 1996. (Spin off) R5000, R7000, etc. Instruction Set

For more information, see MIPS reduction.

Generally, MIPS command systems include mips I; MIPS II; MIPS III and MIPS IV. It is conceivable that the command system is backward compatible. For example, the MIPs II-based code can run on the mip iii and mips iv processors :-)

The following describes how to specify the command and CPU options when using gcc.

-Mcpu = CPU type
Assume the defaults for the Machine Type CPU type when scheduling instructions. The choices for CPU type are 'r2000', 'r3000', 'r4000 ', 'r4400', 'r4600 ',
And 'r6000 '. While picking a specific CPU type will schedule things appropriately for that participant chip, the compiler will not generate any code that does
Not Meet level 1 of the MIPs ISA (Instruction Set architecture) without the '-mips2' or '-mips3' switches being used.
-Mips1
Issue instructions from level 1 of the MIPs Isa. This is the default. 'r3000 'is the default CPU type at this isa level.
-Mips2
Issue instructions from level 2 of the MIPs ISA (branch likely, square root instructions). 'r6000 'is the default CPU type at this isa level.
-Mips3
Issue instructions from Level 3 of the MIPs ISA (64 bit instructions ). 'r4000 'is the default CPU type at this isa level. this option does not change the sizes of any of the C data types.

Readers may find that, for the majority, we should use mips iii or-mips3. Please note that both r5000 and r10000 are extension products of r4000.

The following are some supplements:

* The MIPs command is 32-bit long, even on a 64-bit CPU. This is helpful for understanding local jump commands.

For example, J (target); Jal (target ). The opercode of J and Jal is 6 bits, And the rest 26 is the storage jump offset. Since any command is 32-bit (or 4-byte) align, the maximum scaling space of J and Jal is 2 ^ 28 = 256 m. If your program needs to jump over M, you must use jalr or JR to store your jump address through a GPR register. Since a register is 32 or 64-bit, you have no limits.

* Several digits in the MIPs CPU Sr (Status Register) are very important settings. When we select the command system or use 64-bit mips cpu core in 32 mode (in most cases, don't tell me you're writing 64-bit programs :--)).

Sr [XX]:
1: mips iv Instruction Set usable
0: MIPS IV INSTRUCTION SET UNUSABLE

SR [KX]
SR [SX]
SR [UX]:
0: the CPU is working in 32-Bit mode.
1: The CPU runs in 64-Bit mode.

Generally, if you want to write a 32-bit MIPS program from the beginning, you 'd better set the value to 0. Why is it best? Because I didn't take risks at work, set them to 1, who knows what wowould happen? :-) And then why bother :--)?

* In the future, we will talk about the relationship between pipelines and command systems, especially jump commands. Here, we will simply mention it. For simplity, add an empty transfer command (NOP) to the end of any skip command ). This prevents the cpu pipeline from executing a PRE_FETCH command incorrectly. Of course, this NOP can be replaced with something else. I will talk about it later. It is the simplest and safest to put a NOP. Interested readers can use the mips64-elf-objdump-d to disassemble
OBJECT File. You will be clear at a glance.

* Be sure to remember that the mips I, II, III, and IV command systems do not contain PRIVILEDGED INSTRUCTIONS.

In other words, they are all commands that can be used in user mode (of course, they can also be used in KERNEL ). CPO operations do not belong to the command system.

* Pay attention to ALIGN when the mips cpu is used. MIPS imposes strict requirements on ALIGN. This is a world different from POWERPC. The command must be 32-bit aligned. The data type must be in
The size and boundary are aligned. Simple Example: When CPU running under 32bit mode, int must 32bit aligned; long 32bit aligned; pointer must be 32bit aligned; char must 8 bit aligned. long long must 64 bit aligned; I 've suffered from this. Of course, I know that everyone will make mistakes here: --), even if you know. Some things are useless :--). Be sure to pay attention.

* I suggest you take a look at the definition of the instruction system when reading specification. It is not difficult. Each Command has several fields (fields ).