NAND Flash Driver Design

Abstract: Taking Samsung k9f2808uob as an example, the interface circuit of NAND Flash and S3C2410 is designed.
The Design and Implementation of flash in the ARM embedded system are verified on uboot. The designed driver is easy to transplant and can simplify embedded system development.

Introduction

Currently, in the development and design of various embedded systems, the storage module design is an indispensable and important aspect. Nor and NAND are two major non-loss flash technologies on the market. Nor flash memory has a small capacity and a low write speed. However, due to its fast random reading speed, it is often used to store program code in embedded systems. Compared with nor, the advantage of nand flash memory is its large capacity, but its speed is slow because it has only 8 or 16 I/O Ports, to complete the transmission of addresses and data, these signals must be sent in turn. NAND Flash has a very high unit density. The capacity can be relatively large and the price is relatively low.

This article uses
Taking the k9f2808uob chip as an example, the design of the interface circuit and driver of NAND Flash is introduced. This article introduces the basic principle of developing the NAND Flash Driver, which is intended to simplify the development process of the embedded system.

1. operating principle of NAND Flash

The NAND flash on the S3C2410 board is composed of two parts:
NAND Flash Controller on CPU

And NAND flash storage chips. To access data in NAND Flash, you must use the NAND Flash Controller to send commands. Therefore, NAND Flash is equivalent to a peripheral of S3C2410 and is not located in its memory address zone.

1.1 chip internal storage layout and storage Operation Features

A piece of NAND Flash is a device whose data storage layers are: 1 device = 528; 1 device = 32 pages; 1 page = 512 bytes = data block size (bytes) + OOB block size (16 bytes ). In each page, the last 16 bytes (also known as OOB, out? Of? Band) is used to set the status after the NAND Flash command is executed. The remaining 512 bytes are divided into the first half and the second half. You can use the NAND Flash command 00 h/01 H/50 h to locate the front half, back half, and OOB respectively, and use the built-in pointer of NAND Flash to point to the respective first address.

Storage operations have the following features: The minimum unit for erasure operations is block. each bit of the NAND flash chip can only change from 1 to 0, but not from 0 to 1, therefore, you must erase the corresponding block before writing the block (the bit of the corresponding block is changed to 1); the OOB part is 6th bytes (that is, 517 bytes) indicates whether it is a bad block. If the value is FF, it is not a bad block. Otherwise, it is a bad block. Except for OOB 6th bytes, the first three bytes of OOB are usually used to store the hardware ECC code of NAND Flash.

1.2 NAND Flash Interface Circuit

First, introduce the hardware design of the Development Board. Figure 1 shows the NAND Flash interface circuit. R/B indicates that SW is ready/busy during connection 1 and 2, and nwait can be used to increase the additional wait period for read/write access during connection 2 and 3. Nand has been integrated into the S3C2410 processor.
Flash Controller. Figure 2 shows how the microcontroller connects to NAND Flash.

Figure 1 NAND Flash Interface Circuit

1.3 controller Working Principle

The NAND Flash Controller maps its own special function registers in its special register area (SFR) address space. It writes the Internal commands of the NAND flash chip to its special function registers, this allows you to control the read, test, and programming of the NAND flash chip. Special Function registers include nfconf, nfcmd, nfaddr, nfdata, nfstat, and nfecc.

Figure 2 connection circuit between NAND Flash and S3C2410

2 principle and structure of Flash burning Program

Basic principle: write data in a storage area of SDRAM to the NAND Flash bucket. The program is divided into three layers vertically. Level 1: The primary burn-Write function writes data from a storage area in SDRAM to the NAND Flash bucket. Layer 2: This layer provides page read, write, block erasure, and other functions that operate on NAND Flash. Layer 3: provides core functions for operating special function registers in a specific NAND Flash Controller for Layer 2. This layer is also a function that truly transfers data between SDRAM and NAND Flash. The second layer is the key to the driver design. The following describes the read, write (also known as programming) and erase function codes of the layer.

2.1 NAND Flash read

Function: Read data is operated on pages. When reading data, write the read data command 00 h, enter the address of the page to be read, and then read the data from the data register, finally, perform ECC verification.

Parameter description: block, block number, page number, and buffer point to the starting position in the memory to be read. Return Value 1: read Successful. Return Value 0: Read failed.

Static int nf_readpage (unsigned int block, unsigned int page, unsigned char * buffer ){

Nf_rstecc ();/* initialize ECC */

Nf_nfce_l ();/* select a NAND flash chip */

Nf_cmd (0x00);/* read from Area A * // * a0 ~ A7 (column address )*/

Nf_addr (0);/* a9a16 (page address )*/

Nf_addr (blockpage & 0xff);/* a17a24, (page address )*/

Nf_addr (blockpage> 8) & 0xff);/* A25, (page address )*/

Nf_addr (blockpage> 16) & 0xff);/* Wait for the NAND Flash to be re-prepared */

Readpage ();/* read the entire page, 512 bytes */

Readecc ();/* read the ECC Code */

Readoob ();/* read the OOB block on the page * // * cancel the selected NAND Flash */

Nf_nfce_h ();/* Verify the ECC code and return */

Return (checkecc ())}

2.2 NAND Flash program

Function: Program commands on pages for write operations.

Command code: First, write 00 H (Zone A)/01 H (Zone B)/05 h (Zone C), indicating that the partition is written; write 80 h to start programming mode (write mode), then write the address and data, and write 10 h to end programming. Figure 3 shows the program flowchart.

Figure 3 program Writing Process

Parameter description: block, block number, page, page number, buffer, pointing to the starting position of data to be written into NAND flash in memory; return value 0, write error, return value 1, write successful.

Static int nf_writepage (unsigned int block, unsigned int page, unsigned char * buffer ){

Nf_rstecc ();/* initialize ECC */

Nf_nfce_l ();/* select a NAND flash chip */

Nf_cmd (0x0);/* write from Area */

Nf_cmd (0x80);/* write the first command * // * a0 ~ A7 (column address )*/

Nf_addr (0);/* a9a16 (page address )*/

Nf_addr (blockpage & 0xff);/* a17a24 (page address )*/

Nf_addr (blockpage> 8) & 0xff);/* A25 (page address )*/

Nf_addr (blockpage> 16) & 0xff);/* The write page is 512b to the NAND flash chip */

Wrdata ();/* OOB consists of 16 bytes. Each byte is defined by the programmer. ECC verification code is stored in byte0 byte2, and bad block mark is stored in byte6 */

Wrdata ();/* write the OOB data block of the page */

CMD (0x10);/* end write command */

Waitrb ();/* Wait for the NAND Flash to be in preparation * // * Send the READ command to the NAND Flash */

CMD (0x70 );

If (rddata () & 0x1) {/* if there is an error in writing, it is marked as a bad block. deselect the NAND Flash check */

Markbadblock (Block );

Return 0;

} Else {/* exit normally. Cancel NAND Flash selection */

Return 1 ;}

2.3 NAND Flash erase

Function: block erasure command.

Command code: first write 60 h to enter the erase mode, then enter the block address, and then write d0h, indicating that the erase operation is complete.

Parameter description: block, block number; return value 0; erasure error (if the block is bad, 0 is returned; if the block is erased, 0 is returned). Return Value 1, erased successfully.

Static int nf_eraseblock (unsigned int block) {/* If this block is a bad block, return */

If (nf_isbadblock (Block) return 0;

Nf_nfce_l ();/* select a NAND flash chip */

Nf_cmd (0x60);/* sets the erase mode * // * a9a16 (page address), which is based on block erasure */

Nf_addr (blockpage & 0xff );

Nf_addr (blockpage> 8) & 0xff);/* A25 (page address )*/

Nf_addr (blockpage> 16) & 0xff); nf_cmd (0xd0); waitrb (); cmd (0x70 );

If (rddata () & 0x1) {/* if there is an error, mark it as a bad block, cancel the flash selection */

Markbadblock (Block );

Return 0;

} Else {/* exit, cancel flash selection */

Return 1 ;}

3 ECC Verification Principle and Implementation

Because the process of NAND Flash cannot ensure that the memory array of NAND maintains reliable performance in its life cycle, Bad blocks will be generated during the production and use of NAND. In order to check the data reliability, some bad zone management policies are usually used in the system that uses NAND Flash. The premise of managing bad zones is that the bad zone detection can be performed reliably. If there is no problem with the Operation Sequence and circuit stability, the NAND Flash error generally does not cause the whole block or the page cannot be read or all errors, but the whole page (such as 512 bytes) there are only one or more errors. Common data verification methods include parity and CRC.
In flash processing, ECC is a special verification method. ECC can correct unit errors and detect dual-bit errors, and the calculation speed is very fast. However, it cannot correct errors with more than one digit, and cannot detect errors with more than two digits. ECC generally generates 3-byte ECC verification data for each 256 bytes of raw data. These 3 bytes are divided into two parts: 6-bit column verification and 16-bit row verification, the redundant Location 2 is 1, as shown in table 1.

Table 1 Composition of school inspection data

First, we will introduce the column verification of ECC. As shown in Column checksum generation rule 4 of ECC, "^" indicates "bitwise XOR" operation. Due to the length of the article, the school inspection will not be introduced. Interested readers can refer to the datasheet chip, which can be downloaded free of charge on the Samsung website.

Figure 4 column checksum generation rules

The mathematical expression is:

When data is written to the page of NAND Flash, an ECC checksum is generated every 256 bytes, which is called the original ECC checksum and saved to the OOB data area of the page. When reading data from NAND Flash, an ECC checksum is generated every 256 bytes, which is called a new ECC checksum. During verification, based on the above ECC generation principle, it is not difficult to infer that the original ECC checksum read from the OOB area is bitwise OR different from the new ECC checksum. If the result is 0, it indicates that there is no error (or an error that cannot be detected by ECC). If there is a 3-byte exception or 11-bit 1 in the result, it indicates that there is a single-bit error and it can be corrected; if three bytes are exclusive or only one bit is 1 in the result
An error occurs in the OOB area. In other cases, an error cannot be corrected.

4 uboot function verification

The implementation of uboot's support for NAND Flash is mainly to implement the operation of NAND Flash Under the command line. Commands for implementing NAND Flash are: NAND info, Nand device, Nand read, Nand write, Nand ervice, and NAND bad. The main data structures used are: struct nand_flash_dev and struct nand_chip. The former includes information such as the main chip model, storage capacity, device ID, and I/O bus width, the latter is the information used to perform specific operations on NAND Flash. Because the method of porting the driver to uboot is not the focus of this article, we will not detail it in detail.

Verification Method: use TFTP to download data to SDRAM, and use the NAND read, Nand write, and NAND ervice commands to read, program, and erase NAND Flash. Test results are listed in table 2. Compared with the data in Datasheet, we can conclude that the driver runs well in the system.

Table 2 Test Results

Conclusion

Nowadays, embedded systems are widely used, and memory devices are an essential part of embedded systems. NAND Flash has obvious advantages over other memory devices with a capacity of no more than 4 GB. The driver designed in this article is not based on any operating system and can be easily transplanted to a variety of operating systems and boot loader. It has some practical significance for simplifying embedded system development.