NIOS II Case Hello CS

1 New Project

Create a new project in Quartus II (hello. PRJ)

2 Qsys Hardware System Setup

Open Qsys in Quartus II:

Opening the Qsys interface discovers that there is already a clk_0 under system contents as shown in. To build a minimal system, you must also add some necessary components, such as Nios II processors, JTAG, Onchip_ram, SystemID, and so on.

Add Jtag:

Add Nios II Processor

Add Onchip_ram

Add Pio

Add System ID

Connected to the connections of system contents, clock CLK and reset are connected to CLK and reset for all components, Nios2_qsys Data_master and instruction_master are associated with
Represents the slave bus S1 connection on the onchip_memory2_0. Other peripherals as bus slave are connected to the Nios2_qsys_0 Data_master

Set the interface properties that need to be connected externally to export, where PIO is set to output:

Here the Nios II processor is also set up to have its reset vector and exception vector set to Onchip_mem:

Let the last row create globle reset, automatically assign addresses and interrupt operations:

Many peripherals have interrupt signals, and in our qsys we also need to connect the peripherals in the corresponding IRQ column to the Nios II processor. In the absence of a connection, there is a hollow dot on the corresponding peripheral, and if it goes up, it is not solid.
Small circle, but can fill in the number of a hollow circle, corresponding can write its interrupt priority.

Finally in the generation in the relevant settings, 13.0 simulation and testbench are set to none, otherwise prone to error.

Click Generation for System generation.

3 cases of Qsys

Back to Quartus II, we created a new Verilog source code file called HELLO.V. Then enter the following code;

Module Hello (clk,rst_n,led); input    CLK; input    rst_n; Output   led;     Myqsys u0 (        . CLK_CLK                        (CLK),                        //  clk.clk        . Reset_reset_n                  ( Rst_n),                  //  reset.reset_n        . Pio_external_connection_export (LED)  / /  pio_external_connection.export    ); Endmodule

Then the Myqsys. Qsys and EX2.V files are added to the project

Comprehensive compilation of the project.

Pin assignment, then final synthesis, layout and cabling .....

Building Software Engineering in 4 EDS

Open the EDS software. First, the following Workspace Path Settings dialog box appears, using the default settings and clicking OK to enter the software.

Access to EDS software interface

menu bar Click file? New? Nios II application and BSP from template Create a new template project.

Load the system hardware, which is the Sopcinfo file,

Select a good sopc file, the default is to select the CPU Nios2_qsys, software engineering named EX3SWPRJ, and finally
Then select the Blank Project template and click Finish to complete the project creation.

Create a new main.c file in the EX2 project

Open MAIN.C file for software programming

/** MAIN.C * * Created on:2015-3-30 * Author:administrator*/#include"Alt_types.h"#include"Altera_avalon_pio_regs.h"#include"sys/alt_irq.h"#include"system.h"#include<stdio.h>#include<unistd.h>voidDelayvoid);intMainvoid) {ALT_U8 timer=0; while(1) {printf ("Hello cs! I am NIOS ii! %d\n", timer);d elay (); Timer++;}return 0;}//Delay LettervoidDelayvoid) {alt_u32 i=0; while(I <4000000) {i++;}}

Do not compile the project first, the BSP editor to set certain settings.

To enter the BSP Editor, you need to follow a table to do the settings, after the completion of the click on the Generate button to exit.

The preceding BSP editor is set in accordance with the following requirements. It is also important to note that any changes in hardware engineering (in Quartus II) are recommended to generate the comma again in the BSP editor before compiling software engineering.
This is to ensure that the hardware and software are consistent, otherwise the compilation will fail.

Then go back to the EDS and select Ex2swprj_bsp and EX2SWPRJ, then right-click to select Build Project. This completes the building of the software platform

5 Board level commissioning

Download the SOF file to the FPGA first

In EDS, select Application Engineering, right-click and select Rus as? Niso II Hardware. The first operation usually pops up the run Configuration interface, first selecting the current project and the current software in the Project column.
(elf files in the application Engineering directory).

On the target Connection page, you need to detect the download hardware information. You can click on the Refresh Connections button on the right to the left to see our download line information in the connections, and we need to make the run button in the lower left corner active (that is, lighten and click). Click Run to start the online operation of the software.

Observe the Nios II Console window:

A Hello CS nios II routine has been completed.

                                                                                                                                                                            2015 March 30

                                                                                                                                                                              cslegened

NIOS II Routines Hello CS