NIOS II causes and solutions for CPU reset anomalies

NIOS II causes and solutions for CPU reset anomalies

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Recently in the project with Nios II, found a strange phenomenon, in the Nios II eds software written good Code, burning to write to the chip, the first to be able to run normally, but when I press the reset button on the card, the system is stuck, and can not run again, unless you re-download the program. The analysis system shows that the hardware design of the system and the Nios II CPU system in the QSYS system have no problems. So why is there such a problem, here I first briefly introduce my system:

My system is mainly composed of Nios II strongest board Cpu,sdram, reserved system timer, reserved timestamp timer, System ID, EPCs controller and Jtag_uart. As shown in the following examples:

In the Qsys environment, I began to set the CPU reset vector (reset vector) on the EPCs, and then in the Nios II eds built software engineering, compile, download run no problem, but did not have the FPGA configuration files and code to solidify into the EPCs, So there is a problem with the reset, yes. Later in order to debug convenient, in the Qsys system will be the CPU reset vector also changed to the SDRAM, and then in the Nios II eds software, after the re-generation of the BSP, software compilation, download operation is no problem, but every time I press the reset button on the board, the system is stuck dead, can no longer run.

Remember last year to do graduation design, once for the system containing EPCs is unable to download the problem of the program, when downloading the program, each time the progress is 64% times the following error, "Nios II ' launching New_configuration ' has Ecountered a problem. Dowenloading Elf Process failed. " I believe this error is also the most hated (note, this picture is I downloaded from the Internet, I do the system has been a long time no problem, want to get a picture like this can only Baidu):

On the internet to find a lot of problems, there is said that the SDRAM phase is wrong, this I have indeed met before but since I have the SDRAM clock phase shift set to 90 degrees, I basically did not encounter this problem. There is a problem with the hardware itself, this is not ruled out, but my system is not the case. In the end is Sina blog or Baidu Space in a certain predecessor's article found the answer I forgot. At that time forgot to write down the blog address, just copy the content, saved a Word document. Now this document has been able to search directly in the Baidu Library, respect for the copyright of others, I here only send the article in the Library address:

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Http://wenku.baidu.com/link?url= Yoyixrjxwj0zunljgqdufdlv8wkf1kcxxxcekhgpaulhwlsxpwjr29gxgbxq-ahmrwot6oknsziaddyzrgayb6zrlu8xaahmhiikud3wpnc

His solution is to modify the two bootloader location-related options in the BSP Editor, and uncheck the Allow_code_at_reset and enable_alt_load two options, such as:

This article describes that when creating a Nios II system without the EPCS controller, the two items in the BSP editor are ticked when the project is created in the Nios II eds. When the Nios II system with the EPCS controller is created, the two items in the BSP editor are not checked when the project is created in the Nios II eds. So, when the reset vector is SDRAM, these two options should be checked. For specific reasons, the author finds the original explanation in the relevant manuals provided by Altera in this article.

When I check the two items in the system, I generate the BSP again, then compile, download, and the processor will be able to perform the reset normally.

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Brother Mei

May 26, 2015 in Beijing to core technology

NIOS II causes and solutions for CPU reset anomalies