Nios ii--Experiment 1--hello_world Hardware part

Hello_world

New schematic diagram of hardware development

1. Open Quartus II 11.0, create a new project, File--New project Wizard ..., ignore introduction, click between? Next> go to the next step. Set up engineering working directory, project name respectively. It is important to note that in the engineering work directory, please use English, do not include spaces, etc., or you may have problems when using the Nios II IDE later. Set as shown in 1. Then proceed to the next step.

2, add the existing files, there is no need to add files, directly click? Next> go to the next step. For device setup. What is the board used for? The Cyclone IV family? EP4CE6E22C8 chip, select OK and go to the next step directly. EDA tool Setup, because the project does not carry out simulation, and so on, so do not set up, if you need to Modelsim simulation, in the simulation line, select tool Name? For Modelsim-altera (this is selected based on the version of Modelsim installed), Format (s) is selected as Verilog HDL (this is also selected based on the hardware description language mastered). Click? Next>?, go to the Summary (summary) page, and then click? Finish.

3, New? Block Diagram/schematic File? (Block diagram/schematic). Click? FILE-New: Select the Block diagram/schematic File in design files and click OK.

Qsys Calling Module

1. Start the Qsys tool and make an IP module call. Click? Tools--Qsys, go to the Qsys Setup screen. The system has already added the clock module by default, the name is Clk_0?, here, select Clk_0, right-click, select Rename, change its name to CLK. The following add any module, you want to make a similar name change, change the name of the method is similar, do not repeat the narrative.

2. Add parts of the soft core processor module. Total need to add

Nios II Processor,

On_chipmemory (RAM or ROM),

JTAG UART,

The System ID peripheral these 4 modules. First familiar? Qsys's interface. To the left component library, is a system-provided component libraries, there are some common modules that make up the processor. The right side is the module that has been added to the system, that is, the Nios II soft core processor can be customized according to the specific needs. In the component library search Nios II Processor, double click to configure. The first thing to choose is the type of Nios II core. The core of Nios II Soft core is divided into three types, E-type, S-type and F-type. The e-core occupies the least amount of resources and functions the simplest and slowest. S-type core occupancy resources Secondly, the function and speed are higher than the former, the F-core has the most functions, the fastest, the corresponding occupation of the most resources, select the time according to demand and chip resources to decide, here Select S core. And then click? Finish to end the current configuration.

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1. Add the on-chip memory below to search in the component library? On Chip Memory. Double-click to set. The main settings are data width and total memoy size in size. The data width is set to a width of bits, which is set to 16 bits. Total Memoy size is set on the on-chip resources and needs to be set appropriately based on the chip resources, which is set to 10240 bytes. Click? Finish to end the current configuration.

1. Add the JTAG download Debug interface. Search for the JTAG UART in the component library. Double-click to set. Because the system has no special requirements, the default configuration is selected here. Click? Finish? End the current configuration.

2. Add the System ID module. The system ID is the unique identifier of the system that distinguishes it from other systems. Search in the component library? System ID peripheral, double-click to set. This is done casually, as set to 123. Click? Finish to end the current configuration.

1. Wired, coming right? The related lines in the Connections column are connected by setting up a node. First, the CLK of all modules is connected together.

   Then the on-chip memory On-chip memory S1 and the processor Nios2 Data_master and Instruction_master connected.

   The Jtag Debug Module Jtag_uart avalon_jtag_slave is connected to the data_master of the processor Nios2.

   The System ID module Sysid_qsys Control_slave is connected to the data_master of the processor Nios2.

2. Set the reset signal.

1. The interrupt of the processor Nios2 and the Jtag_uart interrupt are connected.

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2. Make the relevant settings for the soft core. First double-click Nios2 to enter the processor Setup module. Under the core Nios II column, reset vector memory? Exception vector memory? set to ONCHIP_MEMORY.S1.

3. Click? System-Assign Base Addresses, this time will find the lower messages window of the original error all gone, changed to 0 errors,0 Warnings. If this is not the result, go back and follow the steps to check.

4. Click? Save the file, save it here with the name Hello_world.
5. Finally, select the Generation tab, set the Create simulation model to none, and then click Generate below to build. The time is long, everybody waits patiently.

6. When you are finished, click Close, and then close Qsys back to the Quartus II interface.

Schematic Add IP module

2. Adding niosii Cores

   Double-click the empty space in BLOCK1.BDF to open the Symbol dialog box. Select Project

4. Add PLL

   Click Megawizard Plug-in Manager ... in the lower right corner to enter the macro module call interface.

   Select Creat a new custom megafunction variation, click? Next> go to the next step and add the name of the output file to the PLL after the "What name does want for the". Then search for ALTPLL in the search box on the right, select it, this step mainly for the system Add clock module, and then click? Next> into the next step.

   Popup altpll Settings dialog box, where? Where is the frequency of the inclk0 input? In the General section, change the clock to 50MHz.

   Then follow these procedures to set up:

   Then always set the default, always next to the window, click Finish.

   A quartus II IP Files dialog box pops up, click Yes to complete and no action is required. Then click OK in the Symbol dialog box and place the module in BLOCK1.BDF.

6. connecting, adding pins

   Double-click the Open Symbol dialog box, and2 in Name, and add the door.

   Click Select Module to add Pin, right click, select Generate pins for symbol ports.

   Rename the pin as follows:

8. Click? Project-add/remove files in Project ..., click the Browse button after the file name, select the. qsys file, click Add, and then click OK.

10. Configuration Pins

    First, compile, and then use the script file to configure, toolsàtcl scripts;

12. Set up engineering parameters

    Set as configuration device EPCS4

    Set dual-use pins;

14. In general, please be patient for a long time.

Nios ii--Experiment 1--hello_world Hardware part