PCI Specification Study Notes (2)

I discussed MSI/msix with a friend that day. The following is a summary of the discussion:

1. The MSI-X table and PBA structure is too large, msix capability and can only be placed in the configuration space 64-255 this area, so only the table and PBA in the device memory space. Msix capability stores bar numbers and offsets to configure the spatial index table and PBA.

2.

The Message Address field in MSI capability is not defined in the PCI specification, because the PCI specification must support multiple platforms. The definitions of message addresses are different on x86 and on Linux.

3. The MSI "Message address" (64-or 32-bit) on x86 is defined in the Intel System Programming volume,

Solaris uses the base address 0xfee00000 of the local APIC for bitwise OR 8-bit target processor ID, or 1-bit Rh (value 0), or 1-bit DM (value 0 ), the obtained address is the memory address used for device sending interruption.

4. On x86, the definition of MSI "message data" (16 bits) is relatively simple. Solaris uses the edge trigger mode, the delivery mode is fixed, and the last 8 bits are the interrupt vector address. For information about message addresses and message data, see apic_pci_msi_enable_vector for Solaris..



5. note that the low 3 bits of the MSI "message data" must be dynamically modified based on the multiple message enable bit in the MSI control register, therefore, a "message data" register can be shared by a maximum of 32 vectors.

6. MSI capability supports up to 32 vectors, but the 32 vectors share a "Message Address ". On x86, this "Message Address" is used to determine the local APIC sent to which CPU, So 32 vectors can only be bound to the same CPU.

7. msix capability points to the memory space of the bar corresponding to the table and PBA tables. Table contains the "Message Address" and "message data". The format of X86 is exactly the same as that of MSI. PBA indicates whether the interrupted message is to be processed.

8.

I
Theoretically, a maximum of 32 MSI interrupts can be allocated. When the number of vectors is greater than 1, a continuous adjacent vector must be allocated.
Capability: "message data" and "multiple message"
The definition of enable is determined. For Solaris, see the implementation of apic_alloc_msi_vectors.

9.

Theoretically, a device can allocate up to 2 k msix interrupts, and each interrupt vector can be discontinuous, because the table size is expressed in 11-bit binary, each table item has an independent "Message Address" and "message data ". For Solaris, see apic_alloc_msix_vectors.



10.Because each vector corresponds to an independent "Message Address" and "message data", msix allows one device to bind up to 2 k interruptions to different CPUs, when there are enough CPUs, they do not affect each other, so Intel's sriov 1/10g card VF only supports msix rather than MSI.