PLL (phase locked loop) circuit principle

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(i)

PLL (phase locked loop) circuit principle

In the communication machine and other used oscillation circuit, it requires a wide frequency range, and frequency stability is high. No matter how good the LC oscillation circuit, its frequency stability, can not be compared with the crystal oscillation circuit. However, the frequency of the crystal oscillator can hardly be changed in addition to the use of digital circuit dividers . if the PLL (Phase Lock Loop) (Phaselockedloop) technology is used, the frequency stability is also high in addition to the wide range of oscillation frequencies. This technique is often used in radio, television tuner circuits, and on CD turntable circuits.

basic structure of a PLL (phase-locked loop) circuit

Overview of the PLL (phase-locked loop) circuit
Figure 1 shows a basic block diagram of a PLL (phase-locked loop) circuit. The reference signal used is a high-stability crystal oscillator circuit signal.
The center of this circuit is the phase of this device. The phase comparator can combine the reference signal with the VCO (Voltage controlled oscillator ... Voltage-controlled oscillator) phase comparison. If there is a phase difference between the two signals, a phase error signal output is generated.

(The oscillation frequency of the VCO is compared with the reference frequency, and the frequency of the two is consistent by the control of the feedback circuit.) )

Using this error signal, the VCO's oscillation frequency can be controlled so that the phase of the VCO is consistent with the phase (i.e. frequency) of the reference signal.

A PLL (phase-locked loop) enables the frequency of a high frequency oscillator to coincide with the frequency of an integer multiple of the reference frequency. Since the benchmark oscillator is mostly used for crystal oscillator, the frequency stability of the high frequency oscillator can be compared with the crystal oscillator.
As long as it is an integer multiple of the reference frequency, the output of various frequencies can be obtained.
From the basic structure of the PLL (phase-locked loop) in Figure 1, it is known that it is composed of a vco, a phase comparator, a reference frequency oscillator, and a loop filter. Here, it is assumed that the frequency of the reference oscillator is Fr,vco fo.
In this circuit, it is assumed that when the FR>FO is VC0, the oscillation frequency fo is lower than Fr. The output PD of the phase comparator at this time will generate a positive pulse signal as shown in Figure 2, increasing the VCO oscillator frequency. Conversely, if fr<fo, a negative pulse signal is generated.

(This is a comparison of two signals using the edge of the Pulse wave.) If a phase difference exists, a positive or negative pulse output is generated. )
This PD pulse signal through the Loop filter (loopfilter) integral, you can get DC voltage VR, can control the VCO circuit.
The VCO oscillation frequency is increased due to the change in control voltage VR. The result makes fr=f. When the phase of F and F becomes consistent, the PD terminal becomes a high impedance state so that the PLL (phase locked loop) is locked (lock).

How the Phase Comparator works
The phase comparator described here is phase. Frequency comparator (pfc:phase-frequency Comparator) of the type, the latter lsimc145163p will be hidden in this circuit.
This type of phase of the comparator is not only a phase comparison, that is, not only to do the comparison, in the frequency f different occasions, can also be used as a frequency comparator operating principle.
The relationship between the so-called phase difference Benefit and time t is

In cases where only phase detection is done, for example, it may not be possible to distinguish between a delay 300° or a forward 60°. However, in a phase-frequency comparator, if the FR>FO is considered to be a phase delay.

Selection method of loop filter
The time constant of the loop filter has much to do with whether the PLL (phase locked loop) control is good or not. Although the detailed calculation method is not described here, however, when the reference frequency fr is l0khz, the pulse period of the transmission to the loop filter is 0.1mS.
In order to maintain the voltage value of VR and increase the time constant of the loop filter, it is impossible to trace the oscillation frequency change of the VCO. If the time constant is too small, ripple will occur on the VR, which worsens the stability of the PLL (phase locked loop).
Therefore, based on experience, the time constant of the loop filter is chosen about hundreds of times times the period of the reference frequency (1/FR). This option is approximately dozens of Ms.

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Phase-locked loop is a kind of circuit that controls the crystal oscillator to maintain a constant phase relative to the reference signal, which is widely used in digital communication system. At present, the microprocessor or DSP integrated chip lock phase loop, the main function is to configure the on-chip peripheral clock through software, improve the system flexibility and reliability. In addition, due to the use of software-programmable phase-locked loops, the external system processor is designed to allow a lower operating frequency, while the on-chip PLL microprocessor provides a higher system clock. This design can effectively reduce the system's dependence on external clocks and electromagnetic interference, improve the reliability of system startup and operation, and reduce the design requirements of hardware.

The on-chip crystal and phase-locked loop modules of the TMS320F28L2 processor provide clock signals to the cores and peripherals, and control the device's low-power operating mode. The on-chip crystal oscillator module allows 2 ways to provide the device with a clock, either an internal oscillator or an external clock source. If an internal oscillator is used, a quartz crystal must be connected between the two pins of the Xi/xclkin and X2, generally using 30MHz. If an external clock is used, the sender's clock signal can be directly connected to the Xi/xclkin pin, while the X2 is dangling without using an internal oscillator. The crystal oscillator and phase-locked loop module structure is shown in Figure 1.

　Figure 1 Crystal oscillator and phase-locked loop module

The external Xplldis pin allows you to select the system's clock source. When the Xplldis is low, the system uses an external clock or an external crystal oscillator as the system clock, and when the Xplldis is high, the external clock passes the PLL multiplier to provide the system with a clock. The system can select the operating mode and multiplier coefficients of the PLL by the PLL control register. Table 1 lists the phase-locked loop configuration modes.

　Table 1 Phase-locked loop configuration mode

In addition to providing clocks for the c28x core, the phase-locked loop module provides fast and slow 2 peripheral clocks through the system clock output, as shown in Figure 2. The system clock is mainly controlled by external pin Xplldis and phase-locked loop control registers. Thus, in the case of the system adopting an external clock and enabling the PLL (Xplldis=1), the clock of the c28x core can be set by the software.

　　Figure 2 Processor internal clock circuit

If the Xplldis is high, enabling the chip's internal phase-locked loop circuit, the operating frequency of the system can be set through the control register PLLCR software. However, it is important to note that when you change the operating frequency of the system by software, you must wait for the system clock to stabilize before you can proceed with other operations. In addition, peripheral clocks can be enabled via peripheral clock control registers. In specific applications, to reduce system power consumption, unused peripherals are best to disable their clocks . Peripheral clocks include both fast and slow peripherals, which are set by HISPCP and LOSPCP registers, respectively. A specific application for changing PLL multiplier coefficients and peripheral clocks is given below.