Router basics: Description of vro forwarding mechanism changes

Compatibility and resizing

Vertical Network Construction in the industry is usually implemented step by step, from the first-level network to the second-level network, and then to the third-level network. This inherent characteristic also determines the step-by-step construction mode of the IP voice communication network. In the process of step-by-step construction, voice equipment is facing the problem of backward resizing and compatibility. For example, when building a second-level voice network from a province to a city, you must consider the compatibility with the first-level voice network from the perspective of equipment and system, and the compatibility with the original narrow-band voice network, compatibility with the carrier's IP voice network should also be considered, involving compatibility between different types of devices and devices of different vendors; at the same time, it is also necessary to consider the need for a higher number of users in municipal authorities, narrow band user migration, and a third-level voice network expansion from municipal to County. The center switching equipment should have large-scale networking and resizing capabilities.

General CPU stage

The general-purpose CPU is used as a hardware forwarding platform with high flexibility. During the last century of router development, from the end of the 80 s to the 1990s s, almost all routers on the network use CPU as the core forwarding hardware. Because the ultimate forwarding performance of a general CPU is within KPPS, two 155MPOS interfaces are not capable of line rate forwarding. Therefore, aggregation and access layer routers are widely used to provide as much flexibility as possible in scenarios with low performance requirements.

NP processor stage

Because NP has optimized the microcode for the business, its processing capability for specific businesses is greatly improved compared with the traditional CPU. A single NP-piece can achieve 1-6 mpps forwarding performance, the mature NP has been able to achieve the wire speed forwarding capability of the 2G port.

Because the core router composed of NP has great limitations in high-speed port density and scalability of port performance, in recent years, multiple NP distributed forwarding methods have emerged to achieve data exchange at a high density of 2.5G and 1G ports. However, although NP achieves access to these high-speed ports, however, it cannot solve the high-speed data forwarding problem of multiple internal high-speed interfaces. The industry generally regards it as a suitable aggregation layer router for backbone networks.

ASIC chip phase

It is well known that only ASIC chips can provide extremely high forwarding performance and low costs for specific services at the same time. However, because the fixed feature of ASIC has been unable to meet the needs of routers for multi-service support, the original features of ASIC chips cannot be added once they are generated. This is an increasing number of network services, video and voice services, and Internet applications, the scalability of the ASIC chip becomes an insurmountable threshold for its use on the core router, and it is difficult to meet the requirements of various services in the network. Nowadays, the almost endless demand on the core router performance of the core network forces vro manufacturers and research institutions to focus on ASIC. Moreover, 10 Gbit/s ASIC chips are mature and commercially available, which is also an important reason why network equipment vendors can favor ASIC. At the end of the last century, some manufacturers and scientific research institutions began to fully use ASIC to build the core router platform. So far, they have achieved a sound technical system.

For the ASIC platform, the biggest problem is flexible support for multiple businesses. Flexibility support is mainly reflected in two aspects: look-up table technology and multi-service Message recognition and processing capabilities. In recent years, the TCAM triplicate Content Addressable Storage solves the high-speed query problem of various table items in multiple businesses. Its query performance can reach MB per second, that is to say, a 10g port can be searched more than four times per second. Searching for table items such as route tables, ACL security policies, and QoS policies is the core content supported by multiple businesses. At the same time, the high-speed programmable hardware FPGA manufactured by the current hardware technology can process 40g data streams of the packet header, thus providing the possibility of multi-service support. Gangwan network Co., Ltd. saw this possibility and found the theoretical basis for building the hardware platform. After three years of painstaking research, at last, ASIC + FPGA + TCAM is implemented to achieve high-density processing and forwarding of Multi-Service data with Gigabit, 2.5G, and 10G interfaces, FPGA hardware can process and control the query to form a business flow. TCAM searches for various high-speed business flow table items. ASIC is only responsible for large-capacity forwarding of business flows, this enables large-capacity access to high-speed interfaces for multiple business applications; at the same time, a dedicated ASIC is used inside the router to cut the massive data between the high-speed interface board into cells of a specific length to achieve efficient, low-latency, Tb-level large-capacity data exchange. This structure created by PowerHammer series vrouters in harbor not only solves the bottleneck of performance and flexibility, but also has strong scalability. The interface board can be smoothly expanded to 40g interface access, however, the switching network board can be easily expanded to the TB-level without the need to replace the chassis. At present, almost all mainstream high-end core router equipment suppliers in the industry have launched ASIC-based Router products, it indicates that ASIC has become an inevitable direction for the development of core router technology.

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