RTL compiler Synthesis Steps

1 Synthesis steps

1) Search Paths

rc:/> set_attribute lib_search_path Path
rc:/> set_attribute script_search_path Path
rc:/> set_attribute hdl_search_path Path

2) Target Technology Library

　　　　Rc:/> Set_attribute Library Lib_name.lib

　　　-Target Library: Design Compiler uses the target library to build a circuit. During mapping, Design Compiler selects functionally correct gates from the target library. It also calculates the timing of the circuit, using the vendor-supplied timing data for these gates.

3) Loading the HDL Files

-Sequentially: read_hdl file1.v read_hdl file2.v read_hdl file3.v

-Simultaneously: read_hdl {file1.v file2.v file3.v}　

READ_HDL [-v1995 |-v2001 |-sv-vhdl [-library Library_name]|-netlist][-define macro=value ] ... file_list

4) Performing Elaboration

This was only required for top-level design. The elaborate command automatically elaborates the top-level design and all of its references.

5) Applying Constraints

-Operating conditions; Clock waveforms; I/O timing

6) Applying optimization Constraints

7) Performing Synthesis

　　　　Rc:\> synthesize-to_mapped

8) Analyzing the Synthesis Results

-Generate a detailed area report

-Generate a detailed gate selection and area report, use report Gates

-Generate a detailed timing report, including the worst critical path of the current design, use report timing

9) Exporting the Design

-Gate-level netlist rc:/> write_hdl > DESIGN.V

-Design constraints rc:/> write_script > CONSTRAINTS.G

-Constraints in SDC format rc:/> write_sdc > CONSTRAINTS.SDC

Ten) Exiting RTL Compiler

　　　　Quit or exit

2 Recommended Flow

#General Setup#-------------- set_attributer lib_search_path ... Set_attribute Hdl_search_path.#Load the library#------------------------------Set_attribute Library Library_name#load and elaborate the design#------------------------------READ_HDL design.velaborate#Specify timing and design constraints#--------------------------------------READ_SDC Sdc_file#Add optimization Constraints#----------------------------.....#synthesize the design#---------------------synthesize-to_mapped#Analyze Design------------------Report Area report  Timingreport Gates#Export Design#-------------WRITE_HDL >DESSIGN.VMWRITE_SDC>Constraints.sdcwrite_script>CONSTRAINTS.G#export design for EDI#-----------------------Write_design [-basename string] [-gzip_files] [-TCF] [-encounter] [-hierarchical] [design]

3 working in the top-level (root) directory

Root is a special object this contains all other objects represented as a ' tree ' underneath it.

The root object is all present in RTL Compiler and are represented by a "/", as shown in above.

Root attributes contain information about all loaded designs.

RTL compiler synthesis steps