SDRAM timing-advanced reading and ultimate memory Technical Guide

ArticleDirectory

• 1. Chip Initialization
• 2. the row address is valid.
• 3. Column read/write
• 4. data output (read)
• 5. Data Input (write)

General process of SDRAM work

1. First, we know that the memory controller needs to determine a p-bank chip set before addressing the chips in the set. Therefore, a chip selection signal is required. It selects a p-bank chip set at a time (the number varies depending on the bit width ). The selected chip will receive or read data at the same time, so there must be a chip selection signal.

2. Next we will conduct unified L-bank addressing for all selected chips. Currently, the maximum number of L-banks in SDRAM is 4, therefore, two L-Bank address signals (22 = 4) are required ).

3. The last step is to uniformly address the selected chip in rows/columns (storage units. The number of address lines should be designed based on the chip's organizational structure. But under the same capacity, the number of rows remains unchanged, and only the number of columns changes according to the bit width. The larger the bit width, the smaller the number of columns, because the storage units required are reduced.

4. After a storage unit is found, the selected chip must transmit data in a unified manner. Therefore, there must be a data I/O channel with the same bit width, so there must be a corresponding number of data line pins.

SDRAM Internal basic operations and work sequence 1. Chip Initialization

The initial process of SDRAM during startup is as follows:

2. the row address is valid.

After initialization, to address an array in an L-bank, you must first determine the row to make it active and then determine the column. Although slice selection and L-bank addressing are to be performed before, they can be performed simultaneously with the row.

When Cs # And l-bank are fixed, RAS (row address strobe) is also in valid state. At this time, an address line sends a specific line address. Because the row is valid and the corresponding L-bank is valid, the row is also valid.

3. Column read/write

After the row address is determined, it is necessary to address the column address. However, the address line is still the A0-A11 used by the row address (in this example ). That's right. In SDRAM, the row address and column address line are shared. However, how do read/write commands be issued? In fact, there is no clear signal to send read or write commands, but to achieve the purpose of reading/writing through the control of the write status of the chip. Obviously, we # signal is a key. We # The READ command is of course invalid.

The column addressing signal and read/write command are sent at the same time. Although the address line is shared with the row addressing, the CAS (column address strobe, column address selected pulse) signal can distinguish between the operation and column addressing, with the A0-A9, a11 to determine the specific column address.

However, when sending a column read/write command, the interval must be defined as trcd, that is, Ras to CAS delay (RAS to CAS latency ), it can also be understood as a row-based switching cycle, which is determined by the response time of the electronic components of the chip storage array (from one State to another. Trcd is an important time series parameter of SDRAM. It can be adjusted through the BIOS of the motherboard through the beiqiao chip, but it cannot exceed the preset range of the manufacturer. In a broad sense, trcd is measured in units of clock periods (TCK, clock time). For example, if trcd is set to 2, it indicates that the delay period is two clock cycles, specific to the exact time, it depends on the clock frequency.

The sequence diagram of trcd = 3 is as follows:

4. data output (read)

After selecting the column address, you have determined the specific storage unit. The rest is that the data is output to the memory bus through the data I/O channel (DQ. However, after CAS is issued, it takes some time for data to be output. The time from CAS and read command to the first data output is defined as Cl (CAS latency, CAS latency ). Because Cl only appears during read, Cl is also called read latency (RL, read latency ). The unit of Cl is the same as that of trcd, which is the number of clock cycles. The specific time consumed is determined by the clock frequency.

However, CAs are not delivered to the storage unit after the CL cycle. In fact, CAS and Ras arrive at the same time, but the CAS response time is faster. Why? If the chip width is N bits and the number of columns is C, a row address must be n × C storage bodies, and a column address must be n storage bodies. However, the response time of the transistor in the storage body still makes it impossible to trigger the data on the same rising edge as the CAS. It is sure to delay at least one clock cycle.

Due to the size of the chip, the capacity of the capacitor in the storage unit is very small, so the signal must be amplified to ensure its effective identification, this amplification/drive work is the responsibility of the S-AMP, A storage body corresponds to a S-AMP channel. However, it requires a preparation time to ensure the signal transmission strength (voltage comparison must be performed beforehand to determine the logic level ), therefore, from the data I/O bus has data output before a clock rising edge, the data has been transferred to the S-AMP, that is, the data has been triggered, after a certain amount of driving time, the data is finally transmitted to the I/O bus for output. This time is called TAC (access time from CLK, the access time after the clock is triggered ). The unit of TAC is ns. different frequencies are clearly defined, but they must be smaller than one clock cycle. Otherwise, the efficiency will be reduced due to the length of access time. For example, if the clock period of pc133 is 7.5ns, TAC is 5.4ns. It should be emphasized that each data is read with TACs, including in the continuous reading, but the TACs of the second data are started at the same time of the first data transmission.

TAC of CL = 2

The CL value cannot exceed the design specifications of the chip. Otherwise, the memory may be unstable or even fail to be turned on. (players with overclocking should have experience ), and it cannot be changed temporarily before the data is read. The CL cycle is set during the Mrs phase during startup initialization. In bios, users are generally allowed to adjust it, then the BIOS controls the North Bridge Chip to change the information of the CL register in the Mr via the A4-A6 address line at startup.

5. Data Input (write)

The data write operation is also performed after trcd, but Cl is absent at this time (Remember, CL only appears in the read operation). The sequence diagram of row addressing and column addressing is the same as that of the previous one, only when column addressing is performed, we # is in the valid state.

It can be seen that because the data signal is sent by the control end, the chip does not need to make any adjustment when the input, just need to directly transmit it to the data input register, and then the write driver will charge the storage capacitor, therefore, data can be sent at the same time as CAS, that is, the write latency is 0. However, the data is not written into the storage capacitor in real time, because it takes some time to select a pass transistor (just like when reading) and charge the capacitor, therefore, real Data Writing takes a certain period. To ensure reliable data writing, sufficient write/correction time (twr, write recovery time) is set. This operation is also called write back ). Twr occupies at least one clock cycle or a little more (the higher the clock frequency, the more twr occupies the cycle ).