Software encryption technology based on hard disk number and CPU serial number

The CPU serial number is a unique number that is built inside the processor and cannot be modified. It consists of 96 digits. The high 32-bit is the CPU ID used to identify the CPU type. The low 64 bits each processor is different and uniquely represents the processor. The CPU number can be used to identify each processor. To accommodate this new feature, Intel has added two instructions ("read" and "no") and one register bit (the mode specifies the register bit: Model specific register an "MSR") in processing. The read instruction expands the CPUID read instruction. The 96-bit processor serial number can be obtained when the read instruction is executed. The prohibit instruction can prohibit reading of the processor serial number. The MSR bit is set up to match the read and disable of the CPU serial number. The CPU serial number can be read when the MSR bit is "0", when the MSR is "1", only the high 32 bits (that is, the CPU ID) and the low 64 bits are all zero, and the MSR can only be enabled by the Reset CPU.

Implementation code:

void Cwatersavedlg::onbnclickedbutton6 ()
{
TODO: Add control notification Handler code here
unsigned long s1,s2;
unsigned char vendor_id[]= "------------";//CPU provider ID
CString STR1,STR2,STR3;
The following is the assembly language instruction for obtaining the CPU ID
_ASM//Get CPU provider Information
{
XOR Eax,eax//will eax clear 0
CPUID//command to get CPUID
mov dword ptr vendor_id,ebx
mov dword ptr vendor_id[+4],edx
mov dword ptr vendor_id[+8],ecx
}
Str1. Format ("CPU provider id:%s", vendor_id);

_ASM//Get high 32 bits of CPU ID
{
MOV eax,01h
XOR Edx,edx
Cpuid
MOV s2,eax
}
Str2. Format ("%08x-", S2);

_ASM//Get low 64 bits of CPU ID
{
MOV eax,03h
XOR ecx,ecx
XOR Edx,edx
Cpuid
MOV S1,edx
MOV s2,ecx
}
Str3. Format ("%08x-%08x\n", S1,S2);
Str2= "CPU Serial Number:" + str2 + str3;
MessageBox (STR2);
}

Software encryption technology based on hard disk number and CPU serial number