Summary of Chapter 2

# #所有的学习都是建立在8086CPU的基础上的

• About CPU

the composition of the CPU

1. The CPU is composed of an operator, a controller, a register, a bus (including an internal bus and an external bus), etc.
2. Internal bus: The connection between each device within the CPU
3. External bus: Connect the CPU to other devices on the motherboard

How to describe the CPU

1. The CPU is usually described by the word length :

   (1) 16 bits (word length and bit width are the same, all 16 bits)

   (2) Quasi 32-bit CPU (word length 32 bits, bit width 16 bits)

   (3) Super 32-bit CPU (word length 32 bits, bit width 64 bits)

2. CPU word length is the CPU in a unit time to process the number of bits

3. bit width , the CPU passes the external data bus to the memory one can transmit the bit

• About Registers

Composition of Registers

1. 8086 with 14 registers

(1) AX BX CX DX is a general purpose register for storing general data

(2) SI DI BP SP is base address and variable address register

(3) CS SS DS es is a segment register (CS Register : code segment Register, which is used to hold the "segment address" of the code snippet)

(4) The IP fr is the instruction pointer and the flag register (FR is the PSW on the book, that is, the status register, which is part of the CPU) (IP Register: instruction Pointer Register, which holds the offset address of the instruction that the CPU will read in the code snippet)

Supplemental: A status register is used to hold two types of information: A class of state information (condition code) that embodies the results of the current instruction execution, such as whether there is a carry (cf bit), an overflow (ov bit), a positive or negative (SF bit), and a result of 0 ( ZF bit), parity mark bit (P-bit), and the other is the storage control information (PSW: Program status Word register), such as allow interrupt (if bit), trace flag (TF bit), etc.

Note: The following are examples of CS and IP registers to demonstrate ~ ~

2. For compatibility considerations, 8086CPU can handle two different sizes of data at once. A word consists of two bytes, so the high byte and status byte of the word are stored in the memory of the higher 8-bit memory and low 8-bit memory respectively. If the memory is considered as two independent 8-bit memory to use, the two memory is independent of each other .

3. Data partitioning

(1) the basic single byte memory partition

(2) Word two bytes

(3) Double word four bytes

(4) Four words eight bytes

• Assembly Instructions

1. MOV ax,18
2. MOV ah,18
3. Add ax,8
4. MOV ax,bx
5. Add AX,BX
6. mov Ip,ax (equivalent to jmp ax)
7. JMP 3:01b6 (equivalent to MOV cs,3 mov ip,01b6)

Note: The two operand of the instruction should have the same number of bits, cannot operate a 16-bit register and 8-bit register, and cannot deposit data that exceeds the register number

• 8086CPU method of giving physical address

Background: The compilation We are learning is based on 8086CPU, 8086 is 16-bit machine (that is, within 8086, the maximum length of information that can be processed, transmitted, and temporarily stored is 16 bits), but 8086CPU has a 20-bit address bus, So 8086CPU uses a method that is internally synthesized with two 16-bit addresses to form a 20-bit physical address.

1. Two 16-bit addresses provided by the segment address and offset address in the CPU
2. Segment address and offset address are fed into a part called address adder via the internal bus
3. Address Adder synthesizes Two 16-bit addresses into a 20-bit physical address
4. The address Adder sends 20-bit physical addresses to the address bus via the internal bus
5. 20-bit physical address transmitted to memory by address bus

Physical Address = Segment Address x16+ offset address (0~FFFFH)

• Modify the CS, IP instructions

take Page33 's question 2.3 as an example:

Finally, we conclude that:

Note the point :

• Set the initial state of the CPU, that is, the initial state of CS and IP
• The data in the IP register changes the data immediately after the command is read, after executing the instruction (if the instruction involves changes in the data in the IP), the data in the IP is changed again

Outreach : expanding IA32 to 64 (selected from "In-depth computer system")

We're going through a transition that wants an Intel instruction set 64-bit version. Originally proposed by AMD and named X86-64, it is now supported by most of the AMD64 and Intel64 processors. However, the system still runs only the 32-bit versions of these operating systems, but newer versions of Linux and Windows support this expansion.

IA32 expands to 64-bit because the length of the machine defines the range of virtual addresses that the program can use, while the 32-bit word length is the virtual address space of 4GB. For applications that need to handle large datasets such as scientific computing, database, and data mining, the 32-bit word length makes it very difficult for programmers to work. They must use the Out-of-core algorithm to write code.

X86-64

• Pointers and long integers are 64 bits
• General purpose registers expanded from 8 to 16
• Many program states are stored in registers, not on stacks
• If possible, conditional operations are implemented with conditional delivery directives, which can perform better than traditional branch code
• Floating-point operations are implemented using a register-oriented instruction set instead of IA32 supported stack-based methods.

Summary of Chapter 2