Synopsys Tools Introduction

DC ultra--design Compiler the highest version

The core of the complete integrated solution in Synopsys software is the DC ULTRATM, which is also the best level of integrated platform for all designs. DC Ultra adds a comprehensive range of data path and timing optimization techniques, and is proven by industry repeatedly. DC Ultra has unique optimization technology to meet the challenges of today's design. DC Ultra provides fast, advanced data path optimization technology to establish fast critical path timing. In addition, the DC Ultra uses post-layout and optimized cabling techniques to achieve timing convergence quickly and easily. DC Ultra has established a leading position in the industry, and the DC Ultra Integrated engine offers all the functions of DC expert, as well as its unique advantages.

Software that works with DC Ultra has path synthesis, test synthesis and power optimization, static timing and power analysis, and a proven, high-performance design ware library. This is a unique integration of proven technologies that form a complete integrated solution that can meet all of the user's design challenges in the shortest time possible.

Submit the best quality design results for the area and timing of the data path design

Design with high timing requirements to provide the best circuit performance

Integrated with testing and power consumption to deliver the highest design efficiency and commitment to achieve all the integrated goals

Design that requires multiple iterations of the design process to achieve timing closure, and provides a tight interface to the layout and cabling environment to help quickly achieve multiple timing closure of the design

More than 500 integrated libraries for suppliers from more than 50 wafers and libraries

DesignWare Library (designware )

The DesignWare library contains the most commonly used IP outside of the structure, which is necessary for the design and development of Asics and SoCs. When more than 20,005 designers use the Design ware library, you can be confident that all the IP developed here is of the highest quality and easy to use. When a concession is given to a designer, it means that he can access all the integrated and authenticated IPs in the library.

The Design Ware Library contains basic, integrated building blocks that are necessary for designing a chip. Data path units, such as highly optimized adders and multipliers, are the primary components of the DesignWare library, and the Synopsys company has made significant improvements in the timing and area of circuit design. Since last year, the Design Ware Library has been expanded to include a large number of function blocks, including memory, controller, Memory Bist (built-in self-test) solution, Amba on-chip bus solution, DesignWare Star IP microprocessor core, etc. A complete design ware validation library is formed.

Improved the overall quality of the design

provides many IP modules required for SOC design

On-Chip bus (AMBA)

Peripheral

Memory controller

Building Blocks

Verify IP

Low design risk

DFT Compiler

Single-Pass test synthesis

DFT Compilertm is the Synopsys Advanced testing integrated program. DFT compiler the DFT implementation in the Synopsys synthesis process without impeding the requirements of the original function, timing, signal integrity, or power dissipation. DfT compiler includes a one-time pass-through of test synthesis, including the RTL and gate-level DFT design rule checking (DRC), and the monitoring capability of automatic design rule violations. The DFT Compiler can also provide complete integration, from physical compilation (physical Compiler) to physical optimization implementations.

DFT compiler enables designers to quickly and accurately report the design testability and analysis of any test failure in the early stages of the design cycle. In this regard, DFT compiler can help designers achieve their testability design goals without the need for costly design iterations. The DFT Design Rule Checker enables designers to build RTL levels of friendly testing, which can then be easily synthesized in a single pass test synthesis environment. The integration of tests in the physical compilation (physical Compiler) environment enables the prediction of the results of the timing and achieves the goal of the physical optimization scan design.

Shorten the entire design cycle with DFT implementation in the integrated process

The calculation of RTL-level testability in early design improves design efficiency

Eliminates the unpredictability of back-end design

With the prediction of the timing, power consumption and signal integrity results of the implementation, the iterative and schedule risks of the design are greatly reduced.

vcs-- First into the RTL Portal-level verification platform

VCs are the basis for the entire RTL-level verification platform. VCS provides high performance and functionality for verifying the current millions of-door design. VCs leverages smartverification technology to validate design functions more effectively and improve productivity. VCS supports powerful test vector generation, coverage feedback, advanced debugging techniques and a wide range of ASIC vendor products. VCs can be used throughout the design process, whether early design research or functional simulation, or final design completion

VCs improves the level of abstraction for validation and integrates advanced Smartverification technology into a single, open platform that enables designers to complete design validation with confidence. The VCs employs very advanced technologies, including: code that can support Opernvera assertions (OVA), Openvera test vectors (interface veralite), DIRECTC that can embed C + + functions, and the next generation of Cover rate Verification Technology ob served Cov er age and feature coverage validation tool. With these built-in powerful smartverification technology, users can improve the efficiency of validation.

Using smartverification technology to improve verification efficiency
Delivers the highest performance and functionality, dramatically reducing time-to-market
Support for assertion-based (asserion) validation
Measure quality of validation with built-in coverage measurement tools, new observed Cover age and decision coverage measurements
The DIRECTC interface simplifies the use of C + + functions
has been supported by more than 30 ASIC vendors
Stay compliant with more than 22 third-party tools to ensure flexibility
Products are available in the vast majority of Unix and Linux (also including windowsnt) platforms

leda-- Programming Checker
Synopsys's Leda is a programmable code design Rule Checker that provides full-chip mixed language (Verilog and VHDL) processing capabilities to accelerate the development of complex SOC designs. Leda pre-assembled inspection rules greatly enhance the designer's ability to inspect HDL code, including comprehensiveness, emulation, testability, and reusability. With the design rules provided, you can further improve the performance of Synopsys tools such as VCs, design compiler, and formality. Leda's ruleset helps designers share their design experience, pre-check hardware design, and minimize design risk.
With Leda, the simulation and synthesis of hardware design can be pre-checked to eliminate bottlenecks in the design process, where Verilog code design rules ensure optimization by internal or external tool requirements. Leda provides design rules to improve the performance of Synopsys tools.
Support the design of VERILOG/VHDL mixed language
Includes advanced hardware design speculation and hierarchical inspection capabilities to ensure that designers have a regular check of the hardware structure (including clocks, registers, latches)
Includes pre-assembled comprehensive design rule checks and specification sets.
HDL code checks for Synopsys tool performance optimizations to ensure compatibility with the latest features of tools such as design Compiler, VCs, and formality

Reference documents:

[1] Synopsys tool Introduction. Http://group.ednchina.com/GROUP_MES_14596_2674_39112.HTM

(ext.) Synopsys Tool Introduction