Tcl's use in Vivado

http://blog.chinaaet.com/detail/36014

Vivado is the latest Xilinx FPGA design tool that supports the development of FPGA and ZYNQ 7000 in the 7 series. Vivado can be said to be a completely new design compared to the previous Ise design suite. Whether from the interface, settings, algorithms, or from the user's idea of the requirements, are brand-new. Looking at a lot of blog posts, basically using the GUI to create the project, then I will briefly introduce the Vivado script use.

In the ISE design suite, multiple scripts are supported: You can run Perl scripts with Xperl, you can run TCL scripts with Xtclsh, and you can run the design process with Windows batch scripts.

The ISE integrated TCL script interpreter is version 8.4. At the same time, the TCL console in the Ise GUI is not powerful enough, and some components use a different script than Tcl, which makes Tcl scripts not very popular on Ise.

On Vivado, TCL has become the only supported script. Also, all operations have a corresponding TCL script that can be executed. Therefore, mastering the TCL scripting language is of great help in mastering the use of Vivado.

The integrated TCL scripting interpreter on Vivado is version 8.5 and is currently a popular TCL version. The core of Vivado is a script interpreter, and the GUI interface simply encapsulates a variety of script commands into a graphical interface.

The following is a Windows-based platform, using the scripting idea to run Vivado:

• You first need to set the environment variable, add the path to the Vivado in the PATH environment variable, and set the path to the Bin folder, for example C:\Xilinx\Vivado\2014.1\bin
• Under the Windows interface, start, run, enter CMD, and open the Windows command line terminal. There are three options at this time:

1. Enter "Vivado", launch the Vivado GUI interface, and click on the desktop icon to launch Vivado is no different; in fact, directly clicking on the desktop icon is invoking the Windows Batch command to start Vivado
2. Enter "Vivado-mode Batch-source file.tcl" to launch Vivado from the script batch and execute the FILE.TCL file directly after running
3. Enter "Vivado-mode Tcl" to start the TCL Interactive command line.

• Use the third method. Displays the Vivado version after launch, using 2014.1

• Enter the command "info tclversion" to see the version of TCL used by Vivado 8.5

Tcl is a scripting language that makes it easy for users to define their own commands, and Xilinx adds a lot of VIVADO commands on that basis. For Vivado custom non-standard TCL command, after entering this command, continue to enter the space + "-help", you can find the detailed explanation of the command.

The interactive command line functionality of the TCL console and CMD initiates in the Vivado GUI is basically the same, except that Vivado can switch paths more conveniently by using CMD's auto-fill function when switching paths.

Vivado There are two types of design processes: Project Patterns and Non-project mode.

• If you already have a design project, you can use the Tcl script to continue the project process, for example:

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  open_project TEST.xpr    #打开已有的工程文件TEST.xprlaunch_runs synth_1      #运行综合 synth_1wait_on_run synth_1      #等待综合结束launch_runs impl_1 -to_step write_bitstream    #运行实现impl_1，并生成bit文件wait_on_run impl_1       #等待实现结束

  • If you use Non-project mode, the script is more complex, and a template is provided below.

  Note: English notes are reference to Xilinx related documents, Chinese notes are for easy reading, since Vivado native does not support Chinese, so in order to avoid unnecessary errors, it is recommended to remove Chinese

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  ########################################################################################################################################################################################################################################### STEP#1: define the output directory area.# 定义工程文件的存放路径set outputDir ./PRJ# file mkdir $outputDir## STEP#2: setup design sources and constraints## VHDL#read_vhdl -library bftLib [ glob ./Sources/hdl/bftLib/*.vhdl ] #指定需要添加的VHDL库文件，glob是扫描某个路径下的全部文件（这里是.vhdl文件）read_vhdl ./Sources/hdl/bft.vhdl              #指定需要添加的VHDL文件# ############################### Verilog HDL#read_verilog  [ glob ./SRC/*.v ]                #指定需要添加的Verilog文件，glob是扫描某个路径下的全部文件（这里是.v文件）# ############################### XDC#read_xdc [ glob ./CONSTRS/*.xdc ]               #指定需要添加的xdc文件，glob是扫描某个路径下的全部文件（这里是.xdc文件）# ############################### EDIF and NGC#read_edif ../test.edif                          #指定需要添加的网表文件# ############################### IP XCI#read_ip ./CORE/MMCM/MMCM.xci                    #指定需要添加的xci IP文件# ############################### STEP#3: run synthesis, write design checkpoint, report timing,# and utilization estimates# 运行综合 ，同时设定相关综合参数synth_design -top SCRIPT_TEST       \             -part xc7z100ffg900-2  \             -fanout_limit 1000     \             -shreg_min_size 3      \             -flatten_hierarchy fullwrite_checkpoint -force $outputDir/post_synth.dcp #存档report_timing_summary -file $outputDir/post_synth_timing_summary.rpt    #生成时序报告report_utilization -file $outputDir/post_synth_util.rpt #生成资源使用报告### STEP#4: run logic optimization, placement and physical logic optimization,# write design checkpoint, report utilization and timing estimates#opt_design        #优化设计place_design      #布局report_clock_utilization -file $outputDir/clock_util.rpt    #生成资源使用报告write_checkpoint -force $outputDir/post_place.dcp       #存档report_timing_summary -file $outputDir/post_place_timing_summary.rpt #生成时序报告## STEP#5: run the router, write the post-route design checkpoint, report the routing# status, report timing, power, and DRC, and finally save the Verilog netlist.#route_design      #布线write_checkpoint -force $outputDir/post_route.dcp #存档report_route_status -file $outputDir/post_route_status.rpt #报告布线状况report_timing_summary -file $outputDir/post_route_timing_summary.rpt    #生成时序报告report_power -file $outputDir/post_route_power.rpt  #生成功耗报告report_drc -file $outputDir/post_imp_drc.rpt        #运行DRC 生成DRC检查报告# write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true## STEP#6: generate a bitstream#write_bitstream -force $outputDir/SCRIPT_TEST.bit  #生成bit文件 ##########################################################################################################################################################################################################################################

• In addition, when running the Vivado GUI, there will be a. jou file in the path of the project file, which automatically records all the TCL scripts corresponding to the GUI operation, making it easy to find and use.

  About TCL Learning, many online articles, this is only recommended Xilinx related documents

  UG892 describes the Vivado design process, with instructions for TCL scripts in Non-project mode

  Http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug892-vivado-design-flows-overview.pdf

  UG894 describes how to use TCL in Vivado documentation

  Http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug894-vivado-tcl-scripting.pdf

Tcl's use in Vivado