TI c66x DSP Four memory protection issues--memory protection issues for CPU access to external memory (DDR3 or MSM)-Example

In the case of code maintenance, the CPU accesses the external memory space 0x75510c55 address of the COREPAC, that is, the CPU initiates access to that memory to the L2 memory controller of COREPAC, and then L2 the memory controller sends the request to Corepac's XMC module. XMC module According to the configured register (that is, 32bit virtual address to 36-bit physical address mapping and memory rights register, each memory segment size 16M with a register set, each CPU has the same number of such registers) to check whether the address is legitimate, found that the address is not set in any of these registers, that is, XMC the memory as an illegal address, will be reported through the L2 memory controller illegal address access, L2 memory controller through the system event 0X6E = 110来 escalate the error (event 110 illegal access to this class of memory mdmaerror mapping is fixed, refer to Corepac User Guide 9.3 section), the user can register to the event 110 of the exception processing function to do their own things (such as the general is the active DSP other CPU also crash off, so that the entire DSP stop working, so that the site, easy to investigate the problem), the system will set up Mdmaerror registers, The error type is displayed to the user in the Register, as shown in figure Mdmaerr = 0x40000302,lsb 0x02 means privilege error, that is, the CPU has no access to the 0X75510C55 address.

The above checking mechanism is implemented by hardware.

The following explains the 0x75510c55 memory address, when the CPU to access COREPAC external memory, CPU-initiated access is a virtual address of 32bit, so in order to really access the physical address of external memory (such as DDR), Must be mapped to a 36bit physical address by the previously mentioned XMC module. The 0x75510c55 here is the CPU-initiated 32-bit virtual address, XMC will detect that the address is illegal. At the same time by the last picture (see Ti c66x Data manual table 2-2 Memory Map Summary, in fact, the address is reserved, that is, the CPU and any peripherals are not able to access the reserved address, Users also cannot map these reserved addresses to physical addresses. When the CPU accesses these reserved addresses, it will report the error above. So here the user in the XMC register does not use mapping 0x75510c55 address, of course, XMC detection will be considered illegal address.