TSS Task Status Segment

TSS Full Name task State segment refers to the task site information when the task (process) is switched during the process of operating system process management.

 
 2 TSS work details 
TSS plays an important role in the task switching process, through which the tasks are suspended and restored. The so-called task switch is the execution of a task that suspends the current execution, resumes or initiates another task. During the task switching process, the current value of each register in the processor is automatically saved to the TSS specified by the TR (Task Register), then the selection of the TSS for the next task is loaded into the TR; Finally, the values of each register are taken from the TSS specified by TR to each register in the processor.   This shows that the task is switched by preserving a complete image of each register state of the task site in TSS. 
 3 TSS format The basic format of TSS consists of 104 bytes. This 104-byte basic format is immutable, but beyond this, the system software can also define several additional information.   The basic 104 bytes can be divided into five regions, such as Link field area, inner stack pointer area, address map Register area, register save area and other fields. 
(1). Register Save Area   
The Register save area is located within the TSS and is offset from 20H to 5FH for storing general purpose registers, segment registers, instruction pointers, and flag registers. When a TSS corresponding task is executing, the save area is undefined and the current value of these registers is saved in the region when the current task is toggled out.   When the next switch back to the original task, and then restore the value of these registers from the save area, so that the processor reverts to the state before the task swap out, and ultimately enable the task to resume execution.   From the visible, the general register corresponding to a 32-bit double word, instruction pointer and flag register each corresponding to a 32-bit double word, each segment register also corresponds to a 32-bit double word, the segment register in the selection of only 16 bits, arranged double word low 16 bits, high 16 bits unused, generally should be filled with 0. 
 (2). Inner stack pointer area 
for effective protection, the same task uses a different stack at different privilege levels. For example, when you transform from the outer privilege level 3 to the inner privilege level 0 o'clock, the stack used by the task is also transformed from level 3 to the level 0 stack, and when you transform from the inner privilege level 0 to the outer privilege Level 3 o'clock, the stack used by the task is also transformed from a 0-level stack to a 3-level stack. Therefore, a task may have four stacks, corresponding to four privileged levels.   Four stacks require four stack pointers. There are three stack pointers in the inner stack pointer area of the TSS, all 48-bit full pointers (16-bit and 32-bit offsets), pointing to the top of the stack at level 0, 1, and 2, respectively, placed in the TSS where the offset is 4, 12, and 20. When an inward transfer occurs, the appropriate stack pointer is loaded into the SS and ESP registers to transform to the inner stack, and the outer stack pointer is held in the inner stack.   There is no pointer to a level 3 stack, because level 3 is the outermost layer, so any transfer to the inner tier is unlikely to move to level 3. However, when the privilege level is transformed from the inner to the outer layer, the pointer to the inner stack is not saved to the inner stack pointer area of the TSS. In fact, the processor never writes to the region unless the programmer considers changing the value of the zone. This indicates that the inner stack is always considered an empty stack when transferring to the inner layer.   Therefore, the recurrence of the intra-sibling transfer is not allowed, and once a transfer occurs to a certain level of the inner layer, the normal way to return to the outer layers is to match the outer layer back. 
(3). Address Map Register Area   
the mapping from the virtual address space to the linear address space is determined by the GDT and the LDT, and the part associated with the particular task is determined by the LDT, which is determined by the LDTR. If the paging mechanism is used, then the mapping from the linear address space to the physical address space is determined by the control register CR3 that contains the starting physical address of the page catalog table. Therefore, the mapping of the virtual address space to the physical address space associated with a particular task is determined by LDTR and CR3. Obviously, as the task switches, the address mapping relationship also needs to be switched.   [Page] The Address Map register area for TSS consists of a double-word field at offset 1CH (CR3) and a Word field (LDTR) at offset 60H. When the task is switched on, the processor automatically removes the two fields from the TSS to perform the task, loading the registers CR3 and LDTR respectively.   This changes the mapping of the virtual address space to the physical address space. However, when the task is switched on, the processor does not save the contents of the Register CR3 and LDTR of the swap out task to the address Map register area in the TSS. In fact, the processor is never automatically written to the region. Therefore, if the program changes LDTR or CR3, the new value must be artificially saved to the corresponding field in the Address Map register area in the TSS.   This functionality can be achieved through alias technology. 
(4). Link Fields   
The link field is arranged within the TSS with a 0-starting double word, and its height is 16 bits unused.   The 16-bit selection of the TSS descriptor for the previous task is saved when the link is in effect. If the current task is activated by calling a command call or an interrupt/exception between segments, then the Link field holds the TSS selector for the suspended task, and the NT bit in the flag register EFlags is set to 1, making the link field valid.   On return, since the NT flag bit is 1, the return instruction RET or the interrupt return instruction Iret will allow the control to revert to the previous task on the chain as indicated by the link field. 
(5). Other fields   
in order to achieve input/output protection, I/O license bitmaps are used. The I/O license bitmap used by the task is also stored in the TSS as an extended part of the TSS. The word offset at 66H within the TSS is used for the migration of the I/O license bitmap within the TSS (calculated from the beginning of the TSS).   The role of the I/O license bitmap will be described in more detail in a future article. The word offset at 64H within the TSS is a special attribute provided for the task. In 80386, only one attribute, the Debug trap, is defined. The attribute is the lowest bit of the word, denoted by T. The other position of the word is reserved and must be set to 0. When a task switch occurs, if the T-bit of the entry is 1, the debug trap is generated before the first instruction of the new task executes after the task switch is complete. 

TSS task status segment (RPM)