TSS (Task status segment)

1. What is TSS?
Tss stands for task state segment, which refers to the field information of tasks during task (process) switchover during Process Management of the operating system.

 
2 TSS work details
Tss plays an important role in the task switching process. It enables task suspension and recovery. Task Switching means suspending the currently running task, resuming or starting the execution of another task. During task switching, the current values of each register in the processor are automatically saved to the TSS specified by the tr (Task register). Then, the TSS Selection Sub of the next task is loaded into tr. Finally, the value of each register is retrieved from the TSS specified by Tr and sent to each register of the processor. It can be seen that the switching of tasks is realized by saving the complete map of the status of each register in the task field in TSS.
3. the basic format of the TSS task status segment is shown in. The basic format of TSS consists of 104 bytes. The basic 104-byte format is unchangeable, but additional information can be defined by system software. The basic 104 bytes can be divided into five areas: the link field area, the inner layer Stack pointer area, the address ing register area, the register storage area, and other fields.
(1) Register storage area register storage area is located at 20 h to 5 FH offset in the TSS, used to save General registers, segment registers, instruction pointers and sign registers. When the task corresponding to TSS is being executed, the storage area is undefined. When the current task is switched out, the current values of these registers are saved in this area. When the next time you switch back to the original task, the value of these registers will be restored from the saved area, so that the processor can return to the previous status of the task and finally resume the task. As you can see, each general register corresponds to a 32-bit dual-word, each instruction pointer and sign register correspond to a 32-bit dual-word, and each segment register also corresponds to a 32-bit dual-word, in the segment register, the Selection Sub-item is only 16 bits, and the dual characters are arranged as low as 16 bits. The high 16 bits are not used. Generally, it should be set to 0.
(2). The inner Stack pointer area uses different stacks for the same task at different privileged levels to effectively implement protection. For example, when the stack used by the task is changed from Level 3 to level 0, the stack used by the task is also changed from Level 3 to level 0; when the stack used by the task is changed from the inner privilege level 0 to the outer privilege level 3, the stack used by the task is also changed from the level 0 stack to the Level 3 stack. Therefore, a task may have four stacks, corresponding to four privileged levels. Four stacks require four stack pointers. There are three stack pointers in the inner Stack pointer area of TSS. They are all 48-bit full pointers (16-bit selection and 32-bit offset ), point to the top of stacks of level 0, level 1, and level 2 respectively, and store them in the positions starting from 4, 12, and 20 in sequence in TSS. When an internal stack is transferred, the appropriate stack pointer is loaded into the SS and ESP registers to transform to the internal stack. the pointer of the outer stack is stored in the internal stack. No pointer to level 3 stack. Because Level 3 is the outermost layer, any transfer to the inner layer cannot be transferred to Level 3. However, when the privileged level changes from the inner layer to the outer layer, the pointer of the inner layer stack is not saved to the inner layer Stack pointer area of the TSS. In fact, the processor never writes data to the region unless the programmer deems that the value of the region is changed. This indicates that the inner stack is always considered as an empty stack when it is transferred to the inner layer. Therefore, recursion of the same level of inner layer transfer is not allowed. Once a transfer is made to a certain level of inner layer, the normal way to return to the outer layer is to return matched to the outer layer.
(3 ). the ing from the virtual address space to the linear address space in the address ing register area is determined by gdt and LDT, and the part related to the specific task is determined by LDT, while the LDT is determined by ldtr. If the paging mechanism is used, the ing from the linear address space to the physical address space is determined by the control register of the physical address starting from the table containing the page Directory. Therefore, the ing between the virtual address space related to a specific task and the physical address space is determined by ldtr and C3. Obviously, as the task is switched, the address ing relationship also needs to be switched. [Page] The address ing register area of TSS consists of the double-character field (MCM) at the 1ch offset and the word field (ldtr) at the 60 h offset. During task switching, the processor automatically extracts the two fields from the TSS to which the task is to be executed, and loads them to the registers (S3.) and ldtr respectively. In this way, the ing between the virtual address space and the physical address space is changed. However, during task switching, the processor does not save the content of the registers (such as "3" and "ldtr") in the address ing register area in TSS. In fact, the processor never automatically writes to the region. Therefore, if the program changes ldtr or S3. the new value must be manually saved to the corresponding fields in the address ing register area in TSS. You can use the alias technology to implement this function.
(4). the link field is arranged in the double characters starting from 0 in the TSS, and the 16-bit height is not used. When the link function is enabled, the Selection Sub of the TSS descriptor of the previous task is saved in 16 bits. If the current task is activated by calling command call between segments or by interrupting/exception, the link field stores the Selection Sub of the TSS for the suspended task, in addition, the NT bit in the register eflags is set to 1 to make the link field valid. When returning, because the NT flag is 1, the returned command RET or the interrupted return command iret will restore the control to the previous task on the chain as indicated by the link field.
(5) other fields must use an I/O-licensed bitmap for input/output protection. The I/O license bitmap used by the task is also stored in TSS as an extension of TSS. The characters at the 66h offset in the TSS are used to store the offset of the I/O licensed bitmap in the TSS (calculated from the beginning of the TSS ). The role of I/O licensed bitmap will be detailed in future articles. The 64 h offset in the TSS is a special attribute provided for the task. In 80386, only one property is defined, that is, the debugging trap. This attribute is the delimiter of a word, represented by T. The other positions of the word are reserved and must be set to 0. When a task is switched, if the T-bit of the task is 1, a debugging trap occurs after the task is switched to the First Command of the new task is executed.