Verilog (c) Simulation principle

Let's start by introducing an example:

' Timescale 1ns/100ps

Module TB; Module INV_DFF (Clock, Reset_n, DataIn, dataout);

Reg Ck, Rst_n, din;                                                                                      input clock; 

Wire dout;                                                                                                    input reset_n;

//clock  generation                                                                                      input DataIn;

initial   begin                                                                                                Output reg Data_out

               Ck = 0;                                                                                        wire datainv; 

               forever   #10 Ck = ~ck;                                                              always @ (Posedge Clock or Negedge reset_n)

           end                                                                                                                 begin if (~reset_n)

//reset  generation                                                                                                                  data_out <= 1 ' b0;

initial   begin                                                                                                                        else data_out <= DATA_INV;

               rst_n = 1;                                                                                                  End

               #5 rst_n = 0;                                                                               Assign #3 DATAINV = ~ DataIn;

#55 Rst = 1; Endmodule

End

Data input Generation

Initial begin

Din = 0;

#80 Din = 1;

#40 Din = 0;

End

INV_DFF U_INV_DFF (//duv

. Clock (Ck),

. Reset_n (Rst_n),

. DataIn (Din),

. Dataout (Dout),

);

0 Emulation Time: 3 initial processes and one DUV are executed simultaneously. The processes that are executed at the same time are not fixed in their order, and are related to the emulator used, assuming that they are executed at the same time, in the order of the Code.

Executes the statement in clock Generation ck = 0; ~ck. Executes the forever #10 process hangs.

Execute the statement in reset Generation rst_n = 1; #5 process hangs.

Executes the statement in data Input generation DIN = 0; #80 process hangs.

Executes the statement ~datain in the DUV; #3进程挂起. Always @ process hangs. At this point 0 of the simulation time of the statement complete execution, the simulation of the timeline forward.

3 emulation moment: Only one calculation event DATAINV = #3 ~datain; Updates the value of DATAINV. No more compute events are triggered, so the emulation timeline advances.

5 emulation Moment: Executes the statement in reset Generation rst_n = 0; #55 process hangs.

Because of the Rst_n update time, the always @ Process execution in Duv, the Dataout value is updated. No more calculation events are triggered, and the simulation timeline advances.

10 emulation moment: Performs the computed event CK in Clock gneration. Update event firings. #10进程挂起.

Executes the always process in Duv and calculates the event Data_out = 0. Without triggering more events, the simulation timeline advances.

60 emulation Moment: Performs the computed event CK in Clock gneration. Update event firings. #10进程挂起.

Execute the statement in reset Generation rst_n = 1; The process ends.

Executes the always process in Duv, calculates the event Data_out = 1 (the value of Rst_n is already 1). Without triggering more events, the simulation timeline advances.

80 emulation Moment: Performs the computed event CK in Clock gneration. Update event firings. #10进程挂起.

Executes the statement in data Input generation DIN = 1; #40 process hangs.

Executes the always process in Duv, computes the event data_out = Data_inv.

Executes the statement ~datain in the DUV; #3进程挂起. Always @ process hangs. At this point 0 of the simulation time of the statement complete execution, the simulation of the timeline forward.

Simulation time: Is the time value of the simulation time maintenance, used to model the real time of the simulation circuit (simulation time and software execution time is not any connection), when the simulation time to advance to a certain point in time, the point is called the current simulation time, and any future time is called the future simulation time.

Event: Numerical changes in the model, functional simulation is an event-driven simulation, the entire simulation process is organized around the event.

Update event: In the circuit being emulated, any change in the value of the wire mesh or register in any process is considered an update event.

Calculate event: The calculation of the process as a result of the update event, the calculation of the event.

Calculates the cycle-by-cycle triggers between events and update events, driving the progression of simulation time.

A process is an independent execution unit in Verilog, including: Primitive (Primitives), module (moules), initial process block, always process block, continuous assignment statement (assign), asynchronous task (Task). In emulation, all processes are executed sequentially by Verilog semantics, which is the effect of the parallel execution of each process, and the simulation time does not advance until all current processes are executed.

Initial begin

Ck = 0; Forever Ck = ~ck;

End

The example will hang at emulation time 0, because the update time always triggers the calculation event, and the calculation event always triggers the update time.

Timing control in Verilog: Event statement (@), delay statement (#), wait statement (wait).

Uncertainty in Verilog simulation: In the same simulation time, the execution order of the events in several same scheduling modules is arbitrary, and the arbitrary interleaving of the statements between the processes.

Event scheduling for Verilog:

Note: 1, the blocking assignment and the non-blocking assignment are at the same priority, the order of execution is random or with the emulator. 2, the system task is at the lowest priority, at the time of the last execution.

Verilog (c) Simulation principle