Verilog State Machine

Below are the instructions in the help documentation for the official website Quartus.

A state machine was a sequential circuit that advances through a number of States. By default, the Quartus II software automatically infers state machines in your Verilog HDL code by finding variables whos E functionality can is replaced by a state machine without changing the simulated behavior of your design. If you wish to disable automatic inference of state machines in Verilog HDL, set the value of the logic option to OFF.

The Quartus II software infers state machines for all registered, unsigned vector variables that satisfy the following con Ditions:

• The variable is not declared as a module output

• The values assigned to the variable is constant literals, parameters, enums (SystemVerilog), or other state variables.

• The variable has more than and States, in other words, it is assigned at least and distinct values.

• The variable is not a indexed in an expression or referenced as a operand in an arithmetic expression. The latter condition prohibits state transition logic based on arithmetic relationship among the states, for example, next _state <= State + 1.

• The variable have at most one asynchronous reset condition.

If A variable satisfies these conditions, the Quartus II software recognizes the variable as a state machine and report it In the compilation report. Variables that does not meet these conditions is extracted as regular logic and not reported as a state machines.

Note:use parameters or enumeration literals (SystemVerilog) to represent the States of the Your state machine. The Quartus II software uses the names of the parameters or enumeration literals when referring to the states. If you use constant literals to represent states, the Quartus II software uses those constant literals as the names of the States, which often makes for a less intuitive state machine.

The following Verilog HDL example implements a 3-state state machine.

Module State_machine (CLK, in, Reset, out); Input CLK, in, reset; Output [1:0]out; reg [1:0]out; reg [1:0]state; Parameter S0 = 0, S1 = 1, S2 = 2; Always @ Begin case (state) S0:out = 2 ' b01; S1:out = 2 ' B10; S2:out = 2 ' B11; Default:out = 2 ' b00; Endcase End always @ (Posedge CLK or posedge reset) begin if (reset) state <= S0; else case (state) S0:state <= S1; S1:if (in) state <= S2; else state <= S1; S2:if (in) state <= S0; else state <= S1; Endcase End Endmodule

Includes a combinational always construct to model the output logic and a sequential (edge-triggered) a Lways construct to model the state variable. The state variable reg [1:0]state stores the "state" of the state machine. The parameters S0, S1, and s2represent the states of the state machine.

At Power-up, the state machine initializes to the reset state S0. If there were no explicit reset state, the state machine would initialize to the state with value 0, which for this exampl E is also S0. If there were no state with the value 0, the Quartus II software would choose a arbitrary state is the reset state.

For more information, see the following sections of the IEEE STD 1394-2001 IEEE Hardware Description Language Based on the Verilog Hardware Description languagemanual:

• Section 9.2:procedural Assignments

• Section 9.4:conditional statements

• Section 9.5:case statements

• Section 9.7.2:event Control

• Section 9.9.2:always constructs

Verilog State Machine